From 4e6c9f5954b18e4054e7f872d3173c2480fa3a5b Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 17 Jan 2026 17:55:57 +0100 Subject: [PATCH] sb/intel/bd82x6x/early_usb: Add mainboard hook for USB devices Allow the mainboard code to disable USB ports based on GPIO straps, SKU or user configuration. The mainboard code must implement mb_usb20_port_override() in romstage to disable USB ports. Ports that are statically disabled in devicetree cannot be enabled using this method. Change-Id: I0fd01e12c05d633695a5fb19ff804e9dc588d6ed Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91234 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/southbridge/intel/bd82x6x/early_usb.c | 11 ++++++++++- src/southbridge/intel/bd82x6x/early_usb_mrc.c | 12 +++++++++++- src/southbridge/intel/bd82x6x/pch.h | 3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 7bca0bbc49..50b66d5acf 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -10,6 +10,11 @@ #include "pch.h" #include "chip.h" +__weak uint16_t mb_usb20_port_override(void) +{ + return 0x3fff; +} + void early_usb_init(void) { u32 reg32; @@ -68,7 +73,11 @@ void early_usb_init(void) for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - RCBA32(USBPDO) = reg32; + + /* Allow mainboard to disable ports based on SKU or user config */ + reg32 |= ~mb_usb20_port_override(); + + RCBA32(USBPDO) = reg32 & 0x3fff; reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index bf43e263a4..e12ade0287 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -32,6 +32,11 @@ void enable_usb_bar(void) pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } +__weak uint16_t mb_usb20_port_override(void) +{ + return 0x3fff; +} + /* * Translate coreboot native USB port configuration in devicetree * into a format reference code expects: @@ -64,6 +69,10 @@ void southbridge_fill_pei_data(struct pei_data *pei_data) const uint16_t currents[] = { 0x40, 0x80, 0x130, 0, 0, 0, /* 3-5 not seen in MRC */ 0x40, 0x130, 0x40, 0x80}; + + /* Allow mainboard to disable ports based on SKU or user config */ + u16 mb_usb20_enable = mb_usb20_port_override(); + for (unsigned int port = 0; port < ARRAY_SIZE(config->usb_port_config); port++) { uint16_t current = 0; int ocp = config->usb_port_config[port].oc_pin; @@ -84,7 +93,8 @@ void southbridge_fill_pei_data(struct pei_data *pei_data) __func__, port, config->usb_port_config[port].current); } - pei_data->usb_port_config[port][0] = config->usb_port_config[port].enabled; + pei_data->usb_port_config[port][0] = config->usb_port_config[port].enabled && + (mb_usb20_enable & BIT(port)); pei_data->usb_port_config[port][1] = ocp; pei_data->usb_port_config[port][2] = current; } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2fb97f0d60..534251d5e8 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -39,6 +39,9 @@ bool pch_is_mobile(void); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); +/* Optional mainboard hook to do disable additional USB ports + based on SKU or user configuration. Set bit to 0 to disable port. */ +uint16_t mb_usb20_port_override(void); void early_thermal_init(void); void southbridge_configure_default_intmap(void);