From 4d708beba673890fd844c33f2d61a7bd7c8e64ae Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Mon, 29 Jul 2024 20:25:29 +0100 Subject: [PATCH] soc/inte/{adl,mtl}: Move ASPM helper functions to common The ASPM helper functions are the same for all Intel SOCs since Skylake, so move them to common code. Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/83679 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 2 + src/soc/intel/alderlake/fsp_params.c | 118 +--------------- src/soc/intel/common/Kconfig.common | 5 + src/soc/intel/common/block/aspm/Kconfig | 6 + src/soc/intel/common/block/aspm/Makefile.mk | 2 + src/soc/intel/common/block/aspm/aspm.c | 128 ++++++++++++++++++ .../common/block/include/intelblocks/aspm.h | 18 +++ src/soc/intel/meteorlake/Kconfig | 1 + src/soc/intel/meteorlake/fsp_params.c | 71 +--------- 9 files changed, 164 insertions(+), 187 deletions(-) create mode 100644 src/soc/intel/common/block/aspm/Kconfig create mode 100644 src/soc/intel/common/block/aspm/Makefile.mk create mode 100644 src/soc/intel/common/block/aspm/aspm.c create mode 100644 src/soc/intel/common/block/include/intelblocks/aspm.h diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 15f347f755..4f374eba64 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -51,6 +51,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI @@ -84,6 +85,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_CRASHLOG if MAINBOARD_HAS_CHROMEOS + select HAS_INTEL_CPU_ROOT_PORTS select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8a03b05c21..cbfd223d6a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -466,123 +467,6 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) return config; } -/* - * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base - * Specification 1.1. The UPDs and their default values are consistent - * from Skylake through Meteor Lake. However, the default for CPU ports - * differs from PCH ports. Use auto and maximum unless overwritten - * to make the behaviour consistent. - * - * +-------------------+--------------------------+-----------+-----------+ - * | Setting | Option | PCH Ports | CPU Ports | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpEnableCpm | Disabled | [Default] | [Default] | - * | | Enabled | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpAspm | PchPcieAspmDisabled | | | - * | | PchPcieAspmL0s | | | - * | | PchPcieAspmL1 | | | - * | | PchPcieAspmL0sL1 | | [Default] | - * | | PchPcieAspmAutoConfig | [Default] | | - * | | PchPcieAspmMax | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpL1Substates | Disabled | | | - * | | PchPcieL1SubstatesL1_1 | | | - * | | PchPcieL1SubstatesL1_1_2 | | [Default] | - * | | PchPcieL1SubstatesMax | [Default] | | - * |-------------------|--------------------------|-----------|-----------| - * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | | - * | | PchPcieRpPcieSpeedGen1 | | | - * | | PchPcieRpPcieSpeedGen2 | | | - * | | PchPcieRpPcieSpeedGen3 | | | - * | | PchPcieRpPcieSpeedGen4 | | | - * +-------------------+--------------------------+-----------+-----------+ - */ - -static unsigned int adl_aspm_control_to_upd(enum ASPM_control aspm_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(ASPM_DISABLE); - - /* Use auto unless overwritten */ - if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); - - return UPD_INDEX(aspm_control); -} - -static unsigned int adl_l1ss_control_to_upd(enum L1_substates_control l1_substates_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Don't enable UPD if Kconfig not set */ - if (!CONFIG(PCIEXP_L1_SUB_STATE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* L1 Substate should be disabled in compliance mode */ - if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Use maximum unless overwritten */ - if (!l1_substates_control) - return UPD_INDEX(L1_SS_L1_2); - - return UPD_INDEX(l1_substates_control); -} - -static unsigned int adl_pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) -{ - /* Use auto unless overwritten */ - if (!pcie_speed_control) - return UPD_INDEX(SPEED_AUTO); - - return UPD_INDEX(pcie_speed_control); -} - -static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - s_cfg->PcieRpEnableCpm[index] = - get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); - s_cfg->PcieRpAspm[index] = - adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); - s_cfg->PcieRpL1Substates[index] = - adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); - s_cfg->PcieRpPcieSpeed[index] = - adl_pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); -} - -/* - * Starting with Alder Lake, UPDs for Clock Power Management were - * introduced for the CPU root ports. - * - * CpuPcieClockGating: - * Disabled - * Enabled [Default] - * - * CpuPciePowerGating - * Disabled - * Enabled [Default] - * - */ -static void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); - s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; - s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; - s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; - s_cfg->CpuPcieRpAspm[index] = - adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); - s_cfg->CpuPcieRpL1Substates[index] = - adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); -} - /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL SKU's */ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_config *config) diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 7ce93d4593..7cd57438be 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -151,6 +151,11 @@ config SOC_INTEL_CRASHLOG_ON_RESET This will result in a BERT table being populated containing a PMC crashlog record on every boot. +config HAS_INTEL_CPU_ROOT_PORTS + def_bool n + help + Enables helper functions for CPU root ports alongside PCH root ports. + config SOC_INTEL_IOE_DIE_SUPPORT def_bool n help diff --git a/src/soc/intel/common/block/aspm/Kconfig b/src/soc/intel/common/block/aspm/Kconfig new file mode 100644 index 0000000000..bab13570f1 --- /dev/null +++ b/src/soc/intel/common/block/aspm/Kconfig @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_BLOCK_ASPM + bool + help + Intel Processor common ASPM support diff --git a/src/soc/intel/common/block/aspm/Makefile.mk b/src/soc/intel/common/block/aspm/Makefile.mk new file mode 100644 index 0000000000..fe6c71d25a --- /dev/null +++ b/src/soc/intel/common/block/aspm/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ASPM) += aspm.c diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c new file mode 100644 index 0000000000..afdf3f6fae --- /dev/null +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +/* + * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base + * Specification 1.1. The UPDs and their default values are consistent + * from Skylake through Meteor Lake. However, the default for CPU ports + * differs from PCH ports. Use auto and maximum unless overwritten + * to make the behaviour consistent. + * + * +-------------------+--------------------------+-----------+-----------+ + * | Setting | Option | PCH Ports | CPU Ports | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpEnableCpm | Disabled | [Default] | [Default] | + * | | Enabled | | | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpAspm | PchPcieAspmDisabled | | | + * | | PchPcieAspmL0s | | | + * | | PchPcieAspmL1 | | | + * | | PchPcieAspmL0sL1 | | [Default] | + * | | PchPcieAspmAutoConfig | [Default] | | + * | | PchPcieAspmMax | | | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpL1Substates | Disabled | | | + * | | PchPcieL1SubstatesL1_1 | | | + * | | PchPcieL1SubstatesL1_1_2 | | [Default] | + * | | PchPcieL1SubstatesMax | [Default] | | + * |-------------------|--------------------------|-----------|-----------| + * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | | + * | | PchPcieRpPcieSpeedGen1 | | | + * | | PchPcieRpPcieSpeedGen2 | | | + * | | PchPcieRpPcieSpeedGen3 | | | + * | | PchPcieRpPcieSpeedGen4 | | | + * +-------------------+--------------------------+-----------+-----------+ + */ + +static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control) +{ + /* Disable without Kconfig selected */ + if (!CONFIG(PCIEXP_ASPM)) + return UPD_INDEX(ASPM_DISABLE); + + /* Use auto unless overwritten */ + if (!aspm_control) + return UPD_INDEX(ASPM_AUTO); + + return UPD_INDEX(aspm_control); +} + +static unsigned int l1ss_control_to_upd(enum L1_substates_control l1_substates_control) +{ + /* Disable without Kconfig selected */ + if (!CONFIG(PCIEXP_ASPM)) + return UPD_INDEX(L1_SS_DISABLED); + + /* Don't enable UPD if Kconfig not set */ + if (!CONFIG(PCIEXP_L1_SUB_STATE)) + return UPD_INDEX(L1_SS_DISABLED); + + /* L1 Substate should be disabled in compliance mode */ + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) + return UPD_INDEX(L1_SS_DISABLED); + + /* Use maximum unless overwritten */ + if (!l1_substates_control) + return UPD_INDEX(L1_SS_L1_2); + + return UPD_INDEX(l1_substates_control); +} + +static unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) +{ + /* Use auto unless overwritten */ + if (!pcie_speed_control) + return UPD_INDEX(SPEED_AUTO); + + return UPD_INDEX(pcie_speed_control); +} + +void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index) +{ + s_cfg->PcieRpEnableCpm[index] = + get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->PcieRpAspm[index] = + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->PcieRpL1Substates[index] = + l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); + s_cfg->PcieRpPcieSpeed[index] = + pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); +} + +#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) +/* + * Starting with Alder Lake, UPDs for Clock Power Management were + * introduced for the CPU root ports. + * + * CpuPcieClockGating: + * Disabled + * Enabled [Default] + * + * CpuPciePowerGating + * Disabled + * Enabled [Default] + * + */ +void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index) +{ + bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; + s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; + s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; + s_cfg->CpuPcieRpAspm[index] = + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->CpuPcieRpL1Substates[index] = + l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); +} + +#endif // CONFIG(HAS_INTEL_CPU_ROOT_PORTS) diff --git a/src/soc/intel/common/block/include/intelblocks/aspm.h b/src/soc/intel/common/block/include/intelblocks/aspm.h new file mode 100644 index 0000000000..297e128eb2 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/aspm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_ASPM_H +#define SOC_INTEL_COMMON_BLOCK_ASPM_H + +#include + +void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index); + +#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) +void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index); +#endif + +#endif /* SOC_INTEL_COMMON_BLOCK_ASPM_H */ diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 73d68df296..bc0183d442 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -54,6 +54,7 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 3b4fe466d1..f3fec481b4 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -263,76 +264,6 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) return config; } -/* - * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base - * Specification 1.1. The UPDs and their default values are consistent - * from Skylake through Meteor Lake. However, the default for CPU ports - * differs from PCH ports. Use auto and maximum unless overwritten - * to make the behaviour consistent. - * - * +-------------------+--------------------------+-----------+-----------+ - * | Setting | Option | PCH Ports | CPU Ports | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpEnableCpm | Disabled | [Default] | [Default] | - * | | Enabled | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpAspm | PchPcieAspmDisabled | | | - * | | PchPcieAspmL0s | | | - * | | PchPcieAspmL1 | | | - * | | PchPcieAspmL0sL1 | | [Default] | - * | | PchPcieAspmAutoConfig | [Default] | | - * | | PchPcieAspmMax | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpL1Substates | Disabled | | | - * | | PchPcieL1SubstatesL1_1 | | | - * | | PchPcieL1SubstatesL1_1_2 | | [Default] | - * | | PchPcieL1SubstatesMax | [Default] | | - * +-------------------+--------------------------+-----------+-----------+ - */ - -static unsigned int mtl_aspm_control_to_upd(enum ASPM_control aspm_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(ASPM_DISABLE); - - /* Use auto unless overwritten */ - if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); - - return UPD_INDEX(aspm_control); -} - -static unsigned int mtl_l1ss_control_to_upd(enum L1_substates_control l1_substates_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Don't enable UPD if Kconfig not set */ - if (!CONFIG(PCIEXP_L1_SUB_STATE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* L1 Substate should be disabled in compliance mode */ - if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Use maximum unless overwritten */ - if (!l1_substates_control) - return UPD_INDEX(L1_SS_L1_2); - - return UPD_INDEX(l1_substates_control); -} - -static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - s_cfg->PcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->PcieRpAspm[index] = mtl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm); - s_cfg->PcieRpL1Substates[index] = mtl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates); -} - /* * ME End of Post configuration * 0 - Disable EOP.