diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 3535018be9..17025a4f31 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -147,6 +147,7 @@ STAGE0_SRC := $(patsubst %,$(src)/lib/%,$(STAGE0_LIB_SRC)) \
 	      $(STAGE0_MAINBOARD_SRC) $(STAGE0_CHIPSET_SRC)
 
 STAGE0_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE0_SRC)) \
+	      $(patsubst $(obj)/%.c,$(obj)/%.o,$(STAGE0_DYNAMIC_SRC)) \
 	      $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ))
 
 $(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
diff --git a/mainboard/amd/serengeti/Makefile b/mainboard/amd/serengeti/Makefile
index c2d1dde745..02c6f9a5a0 100644
--- a/mainboard/amd/serengeti/Makefile
+++ b/mainboard/amd/serengeti/Makefile
@@ -22,7 +22,6 @@
 			
 STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
-			$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
@@ -33,6 +32,8 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
 			$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
 
+STAGE0_DYNAMIC_SRC :=	$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
+
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
diff --git a/mainboard/gigabyte/m57sli/Makefile b/mainboard/gigabyte/m57sli/Makefile
index 89bf3facea..da0d0b945a 100644
--- a/mainboard/gigabyte/m57sli/Makefile
+++ b/mainboard/gigabyte/m57sli/Makefile
@@ -21,7 +21,6 @@
 
 STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
-			$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
@@ -31,6 +30,8 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \
 
+STAGE0_DYNAMIC_SRC :=	$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
+
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \