diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 76eba43020..7e4647c6e2 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -12,6 +12,7 @@
 
 #define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
 #define GPIO0_DEV  PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
+#define ACPI_DEV   PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
 
 void bootblock_mainboard_early_init(void)
 {
@@ -26,6 +27,11 @@ void bootblock_mainboard_early_init(void)
 	pnp_write_config(GPIO0_DEV, 0xe0, 0x7f);
 	pnp_write_config(GPIO0_DEV, 0xe1, 0x00);
 
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10); /* Enable 3VSBSW#, needed for S3 suspend */
+	pnp_write_config(ACPI_DEV, 0xe7, 0x11); /* HWM reset by LRESET#, 0.5s S3 delay */
+	pnp_write_config(ACPI_DEV, 0xf2, 0x5d); /* Enable RSTOUT[0-2]# and PME */
+
 	nuvoton_pnp_exit_conf_state(GPIO0_DEV);
 
 	/*
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index e84125b720..058ce7644b 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -56,11 +56,7 @@ chip northbridge/intel/sandybridge
 					device pnp 2e.108 on		# GPIO 0
 						drq 0xe1 = 0x80		# GP07 high turns DRAM_LED off
 					end
-					device pnp 2e.a on		# ACPI
-						drq 0xe4 = 0x10 	# Enable 3VSBSW#, needed for S3 suspend
-						drq 0xe7 = 0x11		# HWM reset by LRESET#, 0.5s S3 delay for compatibility
-						drq 0xf2 = 0x5d		# Enable RSTOUT[0-2]# and PME
-					end
+					device pnp 2e.a on end		# ACPI
 					device pnp 2e.b on		# HWM, front panel LED
 						io 0x60 = 0x290		# HWM address
 						io 0x62 = 0		# SB-TSI address (not used)