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UPSTREAM: soc/intel/skylake: Enable Systemagent IMGU

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Camera and Imaging device should be enabled for camera usecase,
FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit)
expose the same as a config option in devicetree.cb

Also remove a redundant assignment for PchCio2Enable.

BUG=None
BRANCH=None
TEST=lspci should list 00:05:00

Change-Id: I8c1a35d1744079be768a985da0a7e8a54b9a268d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2c8a743d1
Original-Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18365
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446760
This commit is contained in:
Rizwan Qureshi 2017-01-13 22:04:11 +05:30 • committed by chrome-bot
commit 4bf670c8ed
2 changed files with 2 additions and 1 deletions
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1
src/soc/intel/skylake/chip.h
View file

@ -205,6 +205,7 @@ struct soc_intel_skylake_config {
/* Camera */
u8 Cio2Enable;
u8 SaImguEnable;
/* eMMC and SD */
u8 ScsEmmcEnabled;

2
src/soc/intel/skylake/chip_fsp20.c
View file

@ -174,6 +174,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SerialIoDevMode));
params->PchCio2Enable = config->Cio2Enable;
params->SaImguEnable = config->SaImguEnable;
params->Heci3Enabled = config->Heci3Enabled;
params->LogoPtr = config->LogoPtr;
@ -186,7 +187,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchLanEnable = config->EnableLan;
params->PchCio2Enable = config->Cio2Enable;
params->SataSalpSupport = config->SataSalpSupport;
params->SsicPortEnable = config->SsicPortEnable;
params->ScsEmmcEnabled = config->ScsEmmcEnabled;