diff --git a/src/mainboard/supermicro/p4dpe/g2/Config b/src/mainboard/supermicro/p4dpe/g2/Config new file mode 100644 index 0000000000..7ff9831c30 --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/Config @@ -0,0 +1,261 @@ + +## Set all of the defaults for an x86 architecture +## +arch i386 + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript cpu/i386/entry16.lds +ldscript cpu/i386/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE +ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE +mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE +ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript arch/i386/lib/id.lds + +## This is the early phase of linuxBIOS startup +## Things are delicate and we test to see if we should +## failover to another image. +mainboardinit northbridge/intel/E7500/reset_test.inc +mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE +mainboardinit southbridge/intel/82801ca/cmos_failover.inc USE_FALLBACK_IMAGE +ldscript arch/i386/lib/failover.lds USE_FALLBACK_IMAGE + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup our mtrrs +## +mainboardinit cpu/i786/earlymtrr.inc + +## +## Setup the serial port +## +mainboardinit superio/winbond/w83627hf/setup_serial.inc +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc +mainboardinit southbridge/intel/82801ca/watchdog_disable.inc + +## +## Reset pci clock for hardware bug work around +## +mainboardinit southbridge/intel/82801ca/smbus.inc +mainboardinit southbridge/intel/82801ca/smbus_write_block.inc +mainboardinit mainboard/supermicro/p4dpe/pci_clk_reset.inc + +## +## Smbus functions +## +mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc +#mainboardinit southbridge/intel/82801ca/smbus_read_block.inc +#mainboardinit southbridge/intel/82801ca/smbus_print_block.inc +mainboardinit mainboard/supermicro/p4dpe/select_i2c_spd.inc + +## +## Setup RAM +## +#mainboardinit ram/dump_northbridge.inc +#mainboardinit sdram/generic_dump_smbus.inc +#mainboardinit sdram/generic_dump_spd.inc +mainboardinit mainboard/supermicro/p4dpe/mainboard_raminit.inc + +## +## Include the secondary Configuration files +## +northbridge intel/E7500 +southbridge intel/82801ca +southbridge intel/82870 +nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 hwmonitor=1 +dir /src/pc80 +dir /src/superio/winbond/w83627hf +dir /src/ram/ +cpu p5 +cpu p6 +cpu i786 + +## +## Build the objects we have code for in this directory. +## +object mainboard.o +#object devices.o +object mptable.o HAVE_MP_TABLE +object irq_tables.o HAVE_PIRQ_TABLE + + +### +### Build options +### + +## +## Location of the DIMM EEPROMS on the SMBUS +## This is fixed into a narrow range by the DIMM package standard. +## +option SMBUS_MEM_DEVICE_START=(0xa << 3) +option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3) +option SMBUS_MEM_DEVICE_INC=1 +option SMBUS_MEM_CHANNEL_OFF=4 + +## +## Customize our winbond superio chip for this motherboard +## +option SIO_BASE=0x2e +option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ + +## +## Build code for the fallback boot +## +option HAVE_FALLBACK_BOOT=1 + +## +## Build code for using cache as RAM +## +#option USE_CACHE_RAM=0 + +## +## Delay timer options +## +option CONFIG_UDELAY_TSC=1 +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + + +## +## Build code to reset the motherboard from linuxBIOS +## +option HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +option HAVE_PIRQ_TABLE=1 + + +## +## Do not build special code to the keyboard +## +option NO_KEYBOARD=1 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +option HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option tabe table +## +option HAVE_OPTION_TABLE=1 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +option SMP=1 +option MAX_CPUS=4 +option MAX_PHYSICAL_CPUS=2 + +## +## Build code to setup a generic IOAPIC +## +option IOAPIC=1 + +## +## MEMORY_HOLE instructs earlymtrr.inc to +## enable caching from 0-640KB and to disable +## caching from 640KB-1MB using fixed MTRRs +## +## Enabling this option breaks SMP because secondary +## CPU identification depends on only variable MTRRs +## being enabled. +## +nooption MEMORY_HOLE + +## +## Figure out which type of linuxBIOS image to build +## If we aren't a fallback image we must be a normal image +## This is useful for optional includes +## +option USE_FALLBACK_IMAGE=0 +expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE + +### +### LinuxBIOS layout values +### + +## ROM_SIZE is the size of boot ROM that this board will use. +option ROM_SIZE=524288 + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +option ROM_IMAGE_SIZE=49152 + +## LinuxBIOS C code runs at this location in RAM +option _RAMBASE=0x00008000 + +## For the trick of using cache as ram +## put the fake ram location at this address +option CACHE_RAM_BASE=0xfff70000 +option CACHE_RAM_SIZE=0x00010000 + +## +## Use a small 8K stack +## +option STACK_SIZE=0x2000 + +## +## Use a small 8K heap +## +option HEAP_SIZE=0x2000 + +## +## Clean up the motherboard id strings +## +option MAINBOARD_PART_NUMBER=P4DP6 +option MAINBOARD_VENDOR=Supermicro + +option UPDATE_MICROCODE=1 +option CPU_FIXUP=1 + +## +## Only use the option table in a normal image +## +expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE - 65536)) +expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*0) + + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE + +## +## Compute a range of ROM that can cached to speed of linuxBIOS, +## execution speed. +## +expr XIP_ROM_SIZE = 65536 +expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE diff --git a/src/mainboard/supermicro/p4dpe/g2/STATUS b/src/mainboard/supermicro/p4dpe/g2/STATUS new file mode 100644 index 0000000000..570b517298 --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/STATUS @@ -0,0 +1,27 @@ +# These are keyword-value pairs. +# a : separates the keyword from the value +# the value is arbitrary text delimited by newline. +# continuation, if needed, will be via the \ at the end of a line +# comments are indicated by a '#' as the first character. +# the keywords are case-INSENSITIVE +owner: Ron Minnich +email: rminnich@lanl.gov +#status: One of unsupported, unstable, stable +status: stable +explanation: +flash-types: Intel 82801CA +payload-types: +# e.g. linux, plan 9, wince, etc. +OS-types: Linux +# e.g. "Plan 9 interrupts don't work on this chipset" +OS-issues: +console-types:serial +# vga is unsupported, unstable, or stable +vga:unsupported +# Last-known-good follows the internationl date standard: day/month/year +last-known-good: 07/02/2003 +Comments: +Links: +Mainboard-revision: +# What other mainboards are like this one? List them here. +AKA: diff --git a/src/mainboard/supermicro/p4dpe/g2/cmos.layout b/src/mainboard/supermicro/p4dpe/g2/cmos.layout new file mode 100644 index 0000000000..69d140c104 --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/cmos.layout @@ -0,0 +1,94 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +396 1 e 1 thermal_monitoring +397 1 e 1 remap_memory_high +400 1 e 1 power_on_after_fail +#402 1 e 2 hda_disk +#403 1 e 2 hdb_disk +#404 1 e 2 hdc_disk +#405 1 e 2 hdd_disk +#408 4 e 9 CPU_clock_speed +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 FallBack +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +#9 15 800MHZ +#9 11 900MHZ +#9 13 1GHZ +#9 9 1.1GHZ +#9 14 1.2GHZ +#9 10 1.3GHZ +#9 12 1.4GHZ +#9 8 1.5GHZ +#9 7 1.6GHZ +#9 3 1.7GHZ +#9 5 1.8GHZ +#9 1 1.9GHZ +#9 6 2.0GHZ +#9 2 2.1GHZ +#9 4 2.2GHZ +#9 0 2.3GHZ + +checksums + +checksum 392 1007 1008 diff --git a/src/mainboard/supermicro/p4dpe/g2/example-fallback.config b/src/mainboard/supermicro/p4dpe/g2/example-fallback.config new file mode 100644 index 0000000000..e4b2a0aff9 --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/example-fallback.config @@ -0,0 +1,104 @@ +## This will make a target directory of ./fallback +## This is relative to where the configuration file resides in the filesystem +target ./p4dpe-g2-fallback + +mainboard supermicro/p4dpe/g2 + +## Build a fallback not a normal image. +option USE_FALLBACK_IMAGE=1 + +## Build an image for a 512KB rom +## ./fallback/romimage is just the last 64KB which we reserve for the fallback image. +option ROM_SIZE=524288 +#option ROM_SIZE=1048576 + +## Select the maximum size the linuxBIOS code can compile to. +## Allow linuxBIOS to be up to 48KB in size +option ROM_IMAGE_SIZE=40960 + + +## +### The Serial Console +## +## Hardware flow control is currently ignored. + +## Enable the Serial Console +option SERIAL_CONSOLE=1 + +## Select the serial console baud rate. +option TTYS0_BAUD=115200 +#option TTYS0_BAUD=57600 +#option TTYS0_BAUD=38400 +#option TTYS0_BAUD=19200 +#option TTYS0_BAUD=9600 +#option TTYS0_BAUD=4800 +#option TTYS0_BAUD=2400 +#option TTYS0_BAUD=1200 + +# Select the serial console base port +option TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +option TTYS0_LCS=0x3 + + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +option DEFAULT_CONSOLE_LOGLEVEL=7 +## At a maximum only compile in this level of debugging +option MAXIMUM_CONSOLE_LOGLEVEL=4 + +## Use the elf bootloader +option USE_ELF_BOOT=1 + +## Select the boot device +option USE_GENERIC_ROM=1 +#option BOOT_FLOPPY=1 +#option USE_SERIAL_FILL_INBUF=1 +#option BOOT_IDE=1 + +# Load etherboot with the elf bootloader +# The payload command is relative the build directory +# So .. is the directory this config file resides in +payload ../lnxieepro100.ebi + + +## +## Cpu Speed +## +option CPU_CLOCK_MULTIPLIER=XEON_X8 +#option CPU_CLOCK_MULTIPLIER=XEON_X9 +#option CPU_CLOCK_MULTIPLIER=XEON_X10 +#option CPU_CLOCK_MULTIPLIER=XEON_X11 +#option CPU_CLOCK_MULTIPLIER=XEON_X12 +#option CPU_CLOCK_MULTIPLIER=XEON_X13 +#option CPU_CLOCK_MULTIPLIER=XEON_X14 +#option CPU_CLOCK_MULTIPLIER=XEON_X15 +#option CPU_CLOCK_MULTIPLIER=XEON_X16 +#option CPU_CLOCK_MULTIPLIER=XEON_X17 +#option CPU_CLOCK_MULTIPLIER=XEON_X18 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X20 +#option CPU_CLOCK_MULTIPLIER=XEON_X21 +#option CPU_CLOCK_MULTIPLIER=XEON_X22 +#option CPU_CLOCK_MULTIPLIER=XEON_X23 + +## +## Select power on after power fail setting +option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON +#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON + diff --git a/src/mainboard/supermicro/p4dpe/g2/example-normal.config b/src/mainboard/supermicro/p4dpe/g2/example-normal.config new file mode 100644 index 0000000000..b8b5bb4e0f --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/example-normal.config @@ -0,0 +1,105 @@ +## This will make a target directory of ./normal +## This is relative to where the configuration file resides in the filesystem +target ./p4dpe-g2-normal + +mainboard supermicro/p4dpe/g2 + +## Build a normal not a fallback image. +option USE_FALLBACK_IMAGE=0 + +## Build an image for a 512KB rom +## ./normal/romimage is the entire rom image except for the last 64KB +## which are reserved for the fallback image. +option ROM_SIZE=524288 +#option ROM_SIZE=1048576 + +## Select the maximum size the linuxBIOS code can compile to. +## Allow linuxBIOS to be up to 48KB in size +option ROM_IMAGE_SIZE=49152 + + +## +### The Serial Console +## +## Hardware flow control is currently ignored. + +## Enable the Serial Console +option SERIAL_CONSOLE=1 + +## Select the serial console baud rate. +option TTYS0_BAUD=115200 +#option TTYS0_BAUD=57600 +#option TTYS0_BAUD=38400 +#option TTYS0_BAUD=19200 +#option TTYS0_BAUD=9600 +#option TTYS0_BAUD=4800 +#option TTYS0_BAUD=2400 +#option TTYS0_BAUD=1200 + +# Select the serial console base port +option TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +option TTYS0_LCS=0x3 + + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +option DEFAULT_CONSOLE_LOGLEVEL=9 +## At a maximum only compile in this level of debugging +option MAXIMUM_CONSOLE_LOGLEVEL=8 + +## Use the elf bootloader +option USE_ELF_BOOT=1 + +## Select the boot device +option USE_GENERIC_ROM=1 +#option BOOT_FLOPPY=1 +#option USE_SERIAL_FILL_INBUF=1 +#option BOOT_IDE=1 + +# Load etherboot with the elf bootloader +# The payload command is relative the build directory +# So .. is the directory this config file resides in +payload ../lnxieepro100.ebi + + +## +## Cpu Speed +## +#option CPU_CLOCK_MULTIPLIER=XEON_X8 +#option CPU_CLOCK_MULTIPLIER=XEON_X9 +#option CPU_CLOCK_MULTIPLIER=XEON_X10 +#option CPU_CLOCK_MULTIPLIER=XEON_X11 +#option CPU_CLOCK_MULTIPLIER=XEON_X12 +#option CPU_CLOCK_MULTIPLIER=XEON_X13 +#option CPU_CLOCK_MULTIPLIER=XEON_X14 +#option CPU_CLOCK_MULTIPLIER=XEON_X15 +#option CPU_CLOCK_MULTIPLIER=XEON_X16 +option CPU_CLOCK_MULTIPLIER=XEON_X17 +#option CPU_CLOCK_MULTIPLIER=XEON_X18 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X19 +#option CPU_CLOCK_MULTIPLIER=XEON_X20 +#option CPU_CLOCK_MULTIPLIER=XEON_X21 +#option CPU_CLOCK_MULTIPLIER=XEON_X22 +#option CPU_CLOCK_MULTIPLIER=XEON_X23 + +## +## Select power on after power fail setting +option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON +#option MAINBOARD_POWER_ON_AFTER_POWER_FAIL=MAINBOARD_POWER_ON + diff --git a/src/mainboard/supermicro/p4dpe/g2/irq_tables.c b/src/mainboard/supermicro/p4dpe/g2/irq_tables.c new file mode 100644 index 0000000000..7fc14a397d --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/irq_tables.c @@ -0,0 +1,53 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*29, /* there can be total 29 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0xf8, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x19, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0x10, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x1,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x2,0x8, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x6, 0}, + {0x2,0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x7, 0}, + {0x1,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x3,0x8, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0x5, 0}, + {0x3,0x10, {{0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}, {0x68, 0xdcb8}}, 0xb, 0}, + {0,0x18, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x4,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x5,0x8, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x3, 0}, + {0x5,0x10, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x2, 0}, + {0x5,0x18, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x1, 0}, + {0x4,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x6,0x8, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x4, 0}, + {0x6,0x10, {{0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}, {0x69, 0xdcb8}}, 0x9, 0}, + {0,0x20, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x10,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x11,0x8, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x8, 0}, + {0x10,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x12,0x8, {{0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}, {0x63, 0xdcb8}}, 0x7, 0}, + {0,0xf0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0x7,0x8, {{0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}, {0x60, 0xdcb8}}, 0xa, 0}, + {0x7,0x10, {{0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}, {0x61, 0xdcb8}}, 0xb, 0}, + {0x7,0x18, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0xc, 0}, + {0,0xe8, {{0x60, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0xe9, {{0, 0xdef8}, {0x63, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + {0,0xea, {{0, 0xdef8}, {0, 0xdef8}, {0x62, 0xdcb8}, {0, 0xdef8}}, 0, 0}, + {0,0xf8, {{0x62, 0xdcb8}, {0x61, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, + } +}; diff --git a/src/mainboard/supermicro/p4dpe/g2/mainboard.c b/src/mainboard/supermicro/p4dpe/g2/mainboard.c new file mode 100644 index 0000000000..8fa71517b4 --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/mainboard.c @@ -0,0 +1,110 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +unsigned long initial_apicid[MAX_CPUS] = +{ + 0, 6, 1, 7 +}; + +#ifndef CPU_CLOCK_MULTIPLIER +#define CPU_CLOCK_MULTIPLIER XEON_X17 +#endif + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +static void set_power_on_after_power_fail(int setting) +{ + switch(setting) { + case MAINBOARD_POWER_ON: + default: + ich3_power_after_power_fail(1); + w83627hf_power_after_power_fail(POWER_ON); + break; + case MAINBOARD_POWER_OFF: + ich3_power_after_power_fail(0); + w83627hf_power_after_power_fail(POWER_OFF); + break; + + } +} + +static void set_thermal_monitoring(int thermal_monitoring) +{ + int tm_high,tm_low; + + rdmsr(MISC_ENABLE,tm_low,tm_high); + if(thermal_monitoring != THERMAL_MONITORING_OFF) { + tm_low |= THERMAL_MONITORING_SET; + } + else { + tm_low &= ~THERMAL_MONITORING_SET; + } + wrmsr(MISC_ENABLE,tm_low,tm_high); + return; +} + +void mainboard_fixup(void) +{ + int cpu_clock_multiplier; + int power_on_after_power_fail; + int thermal_monitoring; + + w83627hf_power_led(LED_ON); + ich3_enable_ioapic(); + p64h2_enable_ioapic(); + p64h2_setup_pcibridge(); + ich3_enable_serial_irqs(); + ich3_enable_ide(1,1); + ich3_rtc_init(); + ich3_lpc_route_dma(0xff); + isa_dma_init(); + ich3_1e0_misc(); + ich3_1f0_misc(); + +#if 0 /* CPU clock option is not presently used */ + cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; + if(get_option(&cpu_clock_multiplier, "CPU_clock_speed")) + cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; + ich3_set_cpu_multiplier(cpu_clock_multiplier); +#endif + + power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + if(get_option(&power_on_after_power_fail, "power_on_after_fail")) + power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + set_power_on_after_power_fail(power_on_after_power_fail); + + thermal_monitoring = THERMAL_MONITORING_OFF; + if(get_option(&thermal_monitoring, "thermal_monitoring")) + thermal_monitoring = THERMAL_MONITORING_OFF; + set_thermal_monitoring(thermal_monitoring); + + return; +} + +void hard_reset(void) +{ + ich3_hard_reset(); +} + diff --git a/src/mainboard/supermicro/p4dpe/g2/mptable.c b/src/mainboard/supermicro/p4dpe/g2/mptable.c new file mode 100644 index 0000000000..6206b8ddb5 --- /dev/null +++ b/src/mainboard/supermicro/p4dpe/g2/mptable.c @@ -0,0 +1,115 @@ +/* generatred by MPTable, version 2.0.15*/ +/* as modified by RGM for LinuxBIOS */ +#include +#include +#include +#include +#include + +void *smp_write_config_table(void *v, unsigned long * processor_map) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "P4DPE "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc, processor_map); + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "PCI "); + smp_write_bus(mc, 5, "PCI "); + smp_write_bus(mc, 6, "PCI "); + smp_write_bus(mc, 7, "PCI "); + smp_write_bus(mc, 8, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + { + struct pci_dev *dev; + uint32_t base; + dev = pci_find_slot(1, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 3, 0x20, base); + } + dev = pci_find_slot(1, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 4, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 5, 0x20, base); + } + dev = pci_find_slot(4, PCI_DEVFN(0x1c,0)); + if (dev) { + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base); + base &= PCI_BASE_ADDRESS_MEM_MASK; + smp_write_ioapic(mc, 8, 0x20, base); + } + } +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# +*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x5, 0x2, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0xf, 0x2, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x8, 0x3, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x9, 0x3, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x7, 0x4, 0x2, 0x10); +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x8, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v, processor_map); +}