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UPSTREAM: soc/intel/braswell: Add int to unsigned

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Fix the following warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=Build for cyan

Change-Id: I3b46d8e0f3ebeae55c71c54d01475b294652505a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1072e7dcc3
Original-Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/456311
This commit is contained in:
Lee Leahy 2017-03-16 17:35:32 -07:00 • committed by chrome-bot
commit 4af90eef23
5 changed files with 9 additions and 7 deletions
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3
src/soc/intel/braswell/chip.c
View file

@ -339,7 +339,8 @@ struct chip_operations soc_intel_braswell_ops = {
.init = soc_init,
};
static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void pci_set_subsystem(device_t dev, unsigned int vendor,
unsigned int device)
{
printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
__FILE__, __func__, dev_name(dev), vendor, device);

2
src/soc/intel/braswell/lpe.c
View file

@ -44,7 +44,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
static void assign_device_nvs(device_t dev, u32 *field, unsigned int index)
{
struct resource *res;

3
src/soc/intel/braswell/pcie.c
View file

@ -159,7 +159,8 @@ static void pcie_enable(device_t dev)
southcluster_enable_dev(dev);
}
static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
static void pcie_root_set_subsystem(device_t dev, unsigned int vid,
unsigned int did)
{
printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
__FILE__, __func__, dev_name(dev), vid, did);

2
src/soc/intel/braswell/southcluster.c
View file

@ -330,7 +330,7 @@ static void hda_work_around(device_t dev)
static int place_device_in_d3hot(device_t dev)
{
unsigned offset;
unsigned int offset;
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));

6
src/soc/intel/braswell/spi.c
View file

@ -90,7 +90,7 @@ typedef struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
unsigned databytes;
unsigned int databytes;
uint8_t *status;
uint16_t *control;
} ich_spi_controller;
@ -290,13 +290,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;