Move the code from northbridgelib.c to pci_device.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@536 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
8d2ed3010b
commit
4ad781a8a6
7 changed files with 75 additions and 121 deletions
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@ -172,7 +172,7 @@ $(obj)/stage0.o $(obj)/stage0.init: $(STAGE0_OBJ)
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#
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STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \
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compute_ip_checksum.o string.o northbridgelib.o
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compute_ip_checksum.o string.o
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STAGE2_ARCH_X86_OBJ = archtables.o linuxbios_table.o udelay_io.o
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STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
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@ -449,6 +449,32 @@ void pci_bus_read_resources(struct device *dev)
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pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
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}
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/**
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* Set resources for the PCI domain.
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*
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* A PCI domain contains the I/O and memory resource address space below it.
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* Set up basic global ranges for I/O and memory. Allocation of sub-resources
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* draws on these top-level resources in the usual hierarchical manner.
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*
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* @param dev The northbridge device.
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*/
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void pci_domain_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Initialize the system-wide I/O space constraints. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->limit = 0xffffUL;
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res->flags =
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IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system-wide memory resources constraints. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->limit = 0xffffffffULL;
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res->flags =
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IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void pci_set_resource(struct device *dev, struct resource *resource)
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{
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resource_t base, end;
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@ -580,6 +606,32 @@ void pci_dev_set_resources(struct device *dev)
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pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
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}
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/**
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* Create a RAM resource, by taking the passed-in size and creating
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* a resource record.
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*
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* @param dev The device.
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* @param index A resource index.
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* @param basek Base memory address in KB.
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* @param sizek Size of memory in KB.
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*/
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void ram_resource(struct device *dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *res;
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if (!sizek)
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return;
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res = new_resource(dev, index);
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res->base = ((resource_t) basek) << 10; /* Convert to bytes. */
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res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */
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res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size);
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}
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void pci_dev_enable_resources(struct device *dev)
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{
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const struct pci_operations *ops;
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@ -1107,6 +1159,22 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned int min_devfn,
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return max;
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}
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/**
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* Support for scan bus from the "tippy top" -- i.e. the PCI domain,
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* not the 0:0.0 device.
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*
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* This function works for almost all chipsets (AMD K8 is the exception).
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*
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* @param dev The PCI domain device.
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* @param max Maximum number of devices to scan.
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* @return TODO
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*/
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unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max)
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{
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/* There is only one link on this device, and it is always link 0. */
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return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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}
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/**
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* Scan a PCI bridge and the buses behind the bridge.
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*
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@ -94,6 +94,12 @@ unsigned pci_find_capability(struct device * dev, unsigned cap);
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struct resource *pci_get_resource(struct device *dev, unsigned long index);
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void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned device);
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void pci_domain_read_resources(struct device *dev);
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void ram_resource(struct device *dev, unsigned long index,
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unsigned long basek, unsigned long sizek);
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unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
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#define PCI_IO_BRIDGE_ALIGN 4096
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#define PCI_MEM_BRIDGE_ALIGN (1024*1024)
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@ -1,26 +0,0 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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void pci_domain_read_resources(struct device *dev);
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void ram_resource(struct device *dev, unsigned long index,
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unsigned long basek, unsigned long sizek);
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unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
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@ -1,92 +0,0 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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/**
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* Set resources for the PCI domain.
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*
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* A PCI domain contains the I/O and memory resource address space below it.
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* Set up basic global ranges for I/O and memory. Allocation of sub-resources
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* draws on these top-level resources in the usual hierarchical manner.
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*
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* @param dev The northbridge device.
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*/
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void pci_domain_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Initialize the system-wide I/O space constraints. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->limit = 0xffffUL;
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res->flags =
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IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system-wide memory resources constraints. */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->limit = 0xffffffffULL;
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res->flags =
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IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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/**
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* Create a RAM resource, by taking the passed-in size and creating
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* a resource record.
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*
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* @param dev The device.
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* @param index A resource index.
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* @param basek Base memory address in KB.
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* @param sizek Size of memory in KB.
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*/
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void ram_resource(struct device *dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *res;
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if (!sizek)
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return;
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res = new_resource(dev, index);
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res->base = ((resource_t) basek) << 10; /* Convert to bytes. */
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res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */
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res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size);
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}
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/**
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* Support for scan bus from the "tippy top" -- i.e. the PCI domain,
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* not the 0:0.0 device.
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*
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* This function works for almost all chipsets (AMD K8 is the exception).
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*
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* @param dev The PCI domain device.
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* @param max Maximum number of devices to scan.
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* @return TODO
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*/
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unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max)
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{
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/* There is only one link on this device, and it is always link 0. */
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return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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}
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@ -25,7 +25,6 @@
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#include <device/pci_ids.h>
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#include <msr.h>
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#include <amd_geodelx.h>
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#include <northbridgelib.h>
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/* Function prototypes */
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extern void chipsetinit(void);
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@ -43,7 +43,6 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <northbridgelib.h>
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#include "i440bx.h"
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#include "statictree.h"
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