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arm: Fix stored PC value when handling exceptions

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ARM processors save the PC value in the Link Register when they handle
and exception, but they store it with an added offset (depending on the
exception type). In order to make crashes easier to read and correctly
support more complicated handlers in libpayload, this patch adjusts the
saved PC value on exception entry to correct for that offset.

(Note: The value that we now store is what ARM calls the "preferred
return address". For most exceptions this is the faulting instruction,
but for software interrupts (SWI) it is the instruction after that. This
is the way most programs like GDB expect the stored PC address to work,
so let's leave it at that.)

Numbers taken from the Architecture Reference Manual at the end of
section B1.8.3.

BRANCH=none
BUG=chrome-os-partner:18390
TEST=Provoked a data abort and an undefined instruction in both coreboot
and depthcharge, confirmed that the PC address was spot on.

Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199844
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Julius Werner 2014-05-14 14:53:18 -07:00 • committed by chrome-internal-fetch
commit 4a914d36bb
2 changed files with 24 additions and 0 deletions
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19
payloads/libpayload/arch/arm/exception_asm.S
View file

@ -45,25 +45,44 @@ exception_table:
1:
mov sp, $0
b exception_common
/* Undefined Instruction (CAREFUL: the PC offset is specific to thumb mode!) */
2:
sub lr, lr, $2
mov sp, $1
b exception_common
/* Software Interrupt (no PC offset necessary) */
3:
mov sp, $2
b exception_common
/* Prefetch Abort */
4:
sub lr, lr, $4
mov sp, $3
b exception_common
/* Data Abort */
5:
sub lr, lr, $8
mov sp, $4
b exception_common
/* (not used) */
6:
mov sp, $5
b exception_common
/* Interrupt */
7:
sub lr, lr, $4
mov sp, $6
b exception_common
/* Fast Interrupt */
8:
sub lr, lr, $4
mov sp, $7
b exception_common

5
src/arch/arm/armv7/exception.c
View file

@ -81,6 +81,7 @@ static void print_regs(uint32_t *regs)
void exception_undefined_instruction(uint32_t *regs)
{
printk(BIOS_ERR, "exception _undefined_instruction\n");
regs[15] -= 2; /* CAREFUL: specific to thumb mode (otherwise 4)! */
print_regs(regs);
dump_stack(regs[13], 512);
die("exception");
@ -97,6 +98,7 @@ void exception_software_interrupt(uint32_t *regs)
void exception_prefetch_abort(uint32_t *regs)
{
printk(BIOS_ERR, "exception _prefetch_abort\n");
regs[15] -= 4;
print_regs(regs);
dump_stack(regs[13], 512);
die("exception");
@ -105,6 +107,7 @@ void exception_prefetch_abort(uint32_t *regs)
void exception_data_abort(uint32_t *regs)
{
printk(BIOS_ERR, "exception _data_abort\n");
regs[15] -= 8;
print_regs(regs);
dump_stack(regs[13], 512);
die("exception");
@ -121,6 +124,7 @@ void exception_not_used(uint32_t *regs)
void exception_irq(uint32_t *regs)
{
printk(BIOS_ERR, "exception _irq\n");
regs[15] -= 4;
print_regs(regs);
dump_stack(regs[13], 512);
die("exception");
@ -129,6 +133,7 @@ void exception_irq(uint32_t *regs)
void exception_fiq(uint32_t *regs)
{
printk(BIOS_ERR, "exception _fiq\n");
regs[15] -= 4;
print_regs(regs);
dump_stack(regs[13], 512);
die("exception");