diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
index 612d2d424e..d6a48a96fc 100644
--- a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
+++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h
@@ -120,6 +120,8 @@
 #define RTC_K_EOSC_RSV_1		(1 << 9)
 #define RTC_K_EOSC_RSV_2		(1 << 10)
 
+#define RTC_EOSC_CALI_TD_8SEC		(6 << 8)
+
 #define TMA_KEY				0x39e
 #define TMA_KEY_MASK			0xFF
 #define TMA_KEY_SHIFT			0
diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c
index 36e29f5a2a..9837df4e59 100644
--- a/src/soc/mediatek/mt8196/mt6685_rtc.c
+++ b/src/soc/mediatek/mt8196/mt6685_rtc.c
@@ -570,6 +570,11 @@ void rtc_boot(void)
 		}
 	}
 
+	/* Set RTC EOSC calibration period = 8sec */
+	rtc_read(RTC_AL_DOW, &rdata);
+	rtc_write(RTC_AL_DOW, rdata | RTC_EOSC_CALI_TD_8SEC);
+	rtc_write_trigger();
+
 	/* Make sure RTC get the latest register info. */
 	rtc_read(RTC_BBPU, &rtc_bbpu);
 	rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);