From 4988f447d766a8cd54ead513f449bfe915a7305d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 11 Mar 2025 23:23:43 +0530 Subject: [PATCH] soc/intel/pantherlake: Correct GPIO Community 3 PIN mapping This commit rectifies a PIN mapping error in GPIO Community 3, introduced by the removal of CPUJTAG PADs from the static ACPI entry. CPUJTAG PADs are reserved for SoC debugging and should not be configured by kernel drivers. To ensure accurate PIN mapping for subsequent GPIO banks, this patch designates the CPUJTAG PAD range as "RSVD" (Reserved) and exposes the corresponding GPIO PIN numbers. This allows other GPIO banks within Community 3 to correctly adjust their offsets. Problem: Prior to this fix, GPP_H0 was incorrectly assigned PIN 0 within GPIO Community 3, deviating from the EDS. Solution: By marking the CPUJTAG range as RSVD, GPP_H0 is now correctly mapped to PIN 15, aligning with the EDS definition. Changes in details: - Corrected the GPI3 to accurately calculate the GPIO PINs. - Renamed CPUJTAG to RSVD (Reserved) and adjusted related definitions. - Updated GPI3 device to reflect the RSVD group, including adding subproperties and correcting group counts. - Modified gpio_defs.h and gpio_soc_defs.h to reflect the RSVD name change and pad count. Change-Id: I9f32b54a8a0218cd993f01ccf5f0bb158877766a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/86825 Reviewed-by: Cliff Huang Reviewed-by: Pranava Y N Reviewed-by: Jayvik Desai Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/acpi/gpio.asl | 43 +++++++++++++++---- .../intel/pantherlake/include/soc/gpio_defs.h | 2 +- .../pantherlake/include/soc/gpio_soc_defs.h | 2 +- 3 files changed, 37 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl index 653f00b72b..fe73b13b78 100644 --- a/src/soc/intel/pantherlake/acpi/gpio.asl +++ b/src/soc/intel/pantherlake/acpi/gpio.asl @@ -27,10 +27,10 @@ Method (GADD, 1, NotSerialized) Local1 = Arg0 - COM1_GRP_PAD_START } /* GPIO Community 3 */ - If (Arg0 >= GPP_H00 && Arg0 <= COM3_GRP_PAD_END) + If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END) { Local0 = PID_GPIOCOM3 - Local1 = Arg0 - GPP_H00 + Local1 = Arg0 - COM3_GRP_PAD_START } /* GPIO Community 4 */ If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END) @@ -438,7 +438,7 @@ Device (GPI1) } } -/* GPIO Community 3: GPP_H, GPP_A, VGPIO3 */ +/* GPIO Community 3: CPUJTAG (reserved), GPP_H, GPP_A, VGPIO3 */ Device (GPI3) { Name (_HID, ACPI_GPIO_HID) @@ -471,7 +471,7 @@ Device (GPI3) Package (0x02) { "intc-gpio-group-count", - NUM_COM3_GROUPS - 1 /* Skip CPUJTAG */ + NUM_COM3_GROUPS }, Package (0x02) @@ -508,6 +508,12 @@ Device (GPI3) ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x04) { + Package (0x02) + { + "intc-gpio-group-0-subproperties", + RSVD + }, + Package (0x02) { "intc-gpio-group-1-subproperties", @@ -527,10 +533,31 @@ Device (GPI3) } } }) - /* - * Don't expose first bank/group in community 3: CPUJTAG because - * CPUJTAG doesn't required to be controlled by kernel pinctrl driver. - */ + /* first bank/group in community 3: RSVD */ + Name (RSVD, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "intc-gpio-group-name", + "RSVD" + }, + + Package (0x02) + { + "intc-gpio-pad-count", + NUM_GRP_RSVD_PADS + }, + + Package (0x02) + { + "intc-gpio-group-offset", + GPP_RSVD_START_OFFSET + } + } + }) /* 2nd bank/group in community 3: GPP_H */ Name (GPPH, Package (0x02) { diff --git a/src/soc/intel/pantherlake/include/soc/gpio_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_defs.h index e9fdc46a2c..2c6a8101d6 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio_defs.h +++ b/src/soc/intel/pantherlake/include/soc/gpio_defs.h @@ -265,7 +265,7 @@ * ref doc: Panther Lake H GPIO Implementation Summary (#817954) */ #define GPP_E_START_OFFSET 0x9a0 -#define GPP_CPUJTAG_START_OFFSET 0x800 +#define GPP_RSVD_START_OFFSET 0x800 #define GPP_H_START_OFFSET 0x8f0 #define GPP_A_START_OFFSET 0xab0 #define GPP_VGPIO3_START_OFFSET 0xc70 diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h index 69f2f7e4ac..49e34e0460 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h @@ -279,7 +279,7 @@ #define GPP_JTAG_TRST_B INC(GPP_DBG_PMODE) #define GPP_DDSP_HPDALV INC(GPP_JTAG_TRST_B) -#define NUM_GRP_CPUJTAG_PADS (GPP_DDSP_HPDALV - GPP_EPD_ON + 1) +#define NUM_GRP_RSVD_PADS (GPP_DDSP_HPDALV - GPP_EPD_ON + 1) /* * +----------------------------+