diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl
index 653f00b72b..fe73b13b78 100644
--- a/src/soc/intel/pantherlake/acpi/gpio.asl
+++ b/src/soc/intel/pantherlake/acpi/gpio.asl
@@ -27,10 +27,10 @@ Method (GADD, 1, NotSerialized)
 		Local1 = Arg0 - COM1_GRP_PAD_START
 	}
 	/* GPIO Community 3 */
-	If (Arg0 >= GPP_H00 && Arg0 <= COM3_GRP_PAD_END)
+	If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END)
 	{
 		Local0 = PID_GPIOCOM3
-		Local1 = Arg0 - GPP_H00
+		Local1 = Arg0 - COM3_GRP_PAD_START
 	}
 	/* GPIO Community 4 */
 	If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END)
@@ -438,7 +438,7 @@ Device (GPI1)
 	}
 }
 
-/* GPIO Community 3: GPP_H, GPP_A, VGPIO3 */
+/* GPIO Community 3: CPUJTAG (reserved), GPP_H, GPP_A, VGPIO3 */
 Device (GPI3)
 {
 	Name (_HID, ACPI_GPIO_HID)
@@ -471,7 +471,7 @@ Device (GPI3)
 			Package (0x02)
 			{
 				"intc-gpio-group-count",
-				NUM_COM3_GROUPS - 1 /* Skip CPUJTAG */
+				NUM_COM3_GROUPS
 			},
 
 			Package (0x02)
@@ -508,6 +508,12 @@ Device (GPI3)
 		ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
 		Package (0x04)
 		{
+			Package (0x02)
+			{
+				"intc-gpio-group-0-subproperties",
+				RSVD
+			},
+
 			Package (0x02)
 			{
 				"intc-gpio-group-1-subproperties",
@@ -527,10 +533,31 @@ Device (GPI3)
 			}
 		}
 	})
-	/*
-	 * Don't expose first bank/group in community 3: CPUJTAG because
-	 * CPUJTAG doesn't required to be controlled by kernel pinctrl driver.
-	 */
+	/* first bank/group in community 3: RSVD */
+	Name (RSVD, Package (0x02)
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package (0x03)
+		{
+			Package (0x02)
+			{
+				"intc-gpio-group-name",
+				"RSVD"
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-pad-count",
+				NUM_GRP_RSVD_PADS
+			},
+
+			Package (0x02)
+			{
+				"intc-gpio-group-offset",
+				GPP_RSVD_START_OFFSET
+			}
+		}
+	})
 	/* 2nd bank/group in community 3: GPP_H */
 	Name (GPPH, Package (0x02)
 	{
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
index e9fdc46a2c..2c6a8101d6 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_defs.h
@@ -265,7 +265,7 @@
  * ref doc: Panther Lake H GPIO Implementation Summary (#817954)
  */
 #define GPP_E_START_OFFSET		0x9a0
-#define GPP_CPUJTAG_START_OFFSET	0x800
+#define GPP_RSVD_START_OFFSET	0x800
 #define GPP_H_START_OFFSET		0x8f0
 #define GPP_A_START_OFFSET		0xab0
 #define GPP_VGPIO3_START_OFFSET		0xc70
diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
index 69f2f7e4ac..49e34e0460 100644
--- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
@@ -279,7 +279,7 @@
 #define GPP_JTAG_TRST_B		INC(GPP_DBG_PMODE)
 #define GPP_DDSP_HPDALV		INC(GPP_JTAG_TRST_B)
 
-#define NUM_GRP_CPUJTAG_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
+#define NUM_GRP_RSVD_PADS	(GPP_DDSP_HPDALV - GPP_EPD_ON + 1)
 
 /*
  * +----------------------------+