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mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO

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This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as
NC to enable S0ix low power entry.

TEST=Build fatcat and check the platform boots without an issue.

Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84957
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This commit is contained in:
Sukumar Ghorai 2024-11-01 11:23:59 -07:00 • committed by Subrata Banik
commit 4953648253
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/fatcat/variants/fatcat/gpio.c
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@ -100,7 +100,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
/* GPP_B24: ESPI_ALERT0_EC_R_N */
PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),
PAD_NC(GPP_B24, NONE),
/* GPP_B25: X1_SLOT_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL),