From 4943cfe4d0d1509a329c8227f0c9988495be4df3 Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Fri, 27 Feb 2026 11:24:15 +0530 Subject: [PATCH] soc/intel/pantherlake: Remove unsupported WCL CPU ID mappings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove WCL_ID_2 through WCL_ID_5 entries from the power mapping table supports a single SKU configuration. Ref=:830097_WCL_PDG_SchChk_Rev1p5 BUG=b:None TEST=Build ocelot and verify that the system boots Change-Id: I95a8069c9b637c35936e6c0e5de257f7acbd8463 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/91448 Reviewed-by: Jérémy Compostella Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/chip.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 0db0b14036..f3058faf33 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -115,10 +115,6 @@ static const struct soc_intel_pantherlake_power_map { { PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 }, { PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 }, { PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, - { PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, }; /* Types of display ports */