commonlib: Move drivers/storage into commonlib/storage
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Lee Leahy
parent
f542aca090
commit
48dbc663d7
31 changed files with 88 additions and 86 deletions
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/*
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* Copyright 2011, Marvell Semiconductor Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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* Copyright 2017 Intel Corporation
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*
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* Controller independent definitions
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DEVICE_SD_MMC_CTRLR_H__
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#define __DEVICE_SD_MMC_CTRLR_H__
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#include <stdint.h>
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/* Error values returned by the storage drivers */
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#define CARD_UNUSABLE_ERR -17 /* Unusable Card */
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#define CARD_COMM_ERR -18 /* Communications Error */
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#define CARD_TIMEOUT -19
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#define CARD_IN_PROGRESS -20 /* operation is in progress */
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struct mmc_command {
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uint16_t cmdidx;
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/* Common commands */
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_APP_CMD 55
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/* MMC specific commands */
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_AUTO_TUNING_SEQUENCE 21
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#define MMC_CMD_ERASE_GROUP_START 35
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#define MMC_CMD_ERASE_GROUP_END 36
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#define MMC_CMD_ERASE 38
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#define MMC_CMD_SPI_READ_OCR 58
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#define MMC_CMD_SPI_CRC_ON_OFF 59
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/* SD specific commands */
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_ERASE_WR_BLK_START 32
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#define SD_CMD_ERASE_WR_BLK_END 33
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/* SD specific APP commands */
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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uint32_t resp_type;
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#define CARD_RSP_PRESENT (1 << 0)
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#define CARD_RSP_136 (1 << 1) /* 136 bit response */
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#define CARD_RSP_CRC (1 << 2) /* expect valid crc */
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#define CARD_RSP_BUSY (1 << 3) /* card may send busy */
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#define CARD_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define CARD_RSP_NONE (0)
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#define CARD_RSP_R1 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
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#define CARD_RSP_R1b (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE| \
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CARD_RSP_BUSY)
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#define CARD_RSP_R2 (CARD_RSP_PRESENT|CARD_RSP_136|CARD_RSP_CRC)
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#define CARD_RSP_R3 (CARD_RSP_PRESENT)
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#define CARD_RSP_R4 (CARD_RSP_PRESENT)
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#define CARD_RSP_R5 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
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#define CARD_RSP_R6 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
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#define CARD_RSP_R7 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE)
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uint32_t cmdarg;
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#define MMC_TRIM_ARG 0x1
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#define MMC_SECURE_ERASE_ARG 0x80000000
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uint32_t response[4];
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uint32_t flags;
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#define CMD_FLAG_IGNORE_INHIBIT 1
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};
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#define SD_SWITCH_CHECK 0
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#define SD_SWITCH_SWITCH 1
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#define SD_DATA_4BIT 0x00040000
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/* SCR definitions in different words */
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#define SD_HIGHSPEED_BUSY 0x00020000
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#define SD_HIGHSPEED_SUPPORTED 0x00020000
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struct mmc_data {
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union {
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char *dest;
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const char *src;
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};
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uint32_t flags;
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#define DATA_FLAG_READ 1
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#define DATA_FLAG_WRITE 2
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uint32_t blocks;
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uint32_t blocksize;
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};
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struct sd_mmc_ctrlr {
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int (*send_cmd)(struct sd_mmc_ctrlr *ctrlr,
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struct mmc_command *cmd, struct mmc_data *data);
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void (*set_ios)(struct sd_mmc_ctrlr *ctrlr);
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void (*tuning_start)(struct sd_mmc_ctrlr *ctrlr, int retune);
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int (*is_tuning_complete)(struct sd_mmc_ctrlr *ctrlr, int *successful);
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int initialized;
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unsigned int version;
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uint32_t voltages;
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_VDD_165_195_SHIFT 7
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uint32_t clock_base; /* Controller's base clock */
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uint32_t f_min;
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uint32_t f_max;
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uint32_t request_hz; /* Desired clock frequency */
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uint32_t bus_hz; /* Actual bus clock frequency */
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#define CLOCK_KHZ 1000
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#define CLOCK_MHZ (1000 * CLOCK_KHZ)
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#define CLOCK_20MHZ (20 * CLOCK_MHZ)
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#define CLOCK_25MHZ (25 * CLOCK_MHZ)
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#define CLOCK_26MHZ (26 * CLOCK_MHZ)
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#define CLOCK_50MHZ (50 * CLOCK_MHZ)
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#define CLOCK_52MHZ (52 * CLOCK_MHZ)
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#define CLOCK_200MHZ (200 * CLOCK_MHZ)
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uint32_t bus_width;
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uint32_t caps;
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/* Generic controller & driver capabilities. Controller specific capabilities
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* start at 0x00010000
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*/
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#define DRVR_CAP_4BIT 0x00000001
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#define DRVR_CAP_8BIT 0x00000002
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#define DRVR_CAP_AUTO_CMD12 0x00000004
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#define DRVR_CAP_HC 0x00000008
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#define DRVR_CAP_HS 0x00000010
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#define DRVR_CAP_HS52 0x00000020
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#define DRVR_CAP_HS200 0x00000040
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#define DRVR_CAP_HS400 0x00000080
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#define DRVR_CAP_ENHANCED_STROBE 0x00000100
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#define DRVR_CAP_REMOVABLE 0x00000200
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#define DRVR_CAP_DMA_64BIT 0x00000400
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#define DRVR_CAP_HS200_TUNING 0x00000800
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uint32_t b_max;
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uint32_t timing;
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#define BUS_TIMING_LEGACY 0
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#define BUS_TIMING_MMC_HS 1
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#define BUS_TIMING_SD_HS 2
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#define BUS_TIMING_UHS_SDR12 3
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#define BUS_TIMING_UHS_SDR25 4
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#define BUS_TIMING_UHS_SDR50 5
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#define BUS_TIMING_UHS_SDR104 6
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#define BUS_TIMING_UHS_DDR50 7
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#define BUS_TIMING_MMC_DDR52 8
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#define BUS_TIMING_MMC_HS200 9
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#define BUS_TIMING_MMC_HS400 10
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#define BUS_TIMING_MMC_HS400ES 11
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uint32_t mdelay_before_cmd0;
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uint32_t mdelay_after_cmd0;
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uint32_t udelay_wait_after_cmd;
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};
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/* SOC specific routine to override ctrlr->caps and .voltages
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*
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* Set/clear the necessary DRVR_CAP_xxx bits in ctrlr->caps to specify the
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* controllers capabilities and driver workarounds.
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*
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* Set/clear the necessary MMC_VDD_xxx bits in ctrlr->voltages to specify the
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* controllers power support.
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*/
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void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr);
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/* Optional routines to support logging */
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void sdhc_log_command(struct mmc_command *cmd);
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void sdhc_log_command_issued(void);
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void sdhc_log_response(uint32_t entries, uint32_t *response);
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void sdhc_log_ret(int ret);
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#endif /* __DEVICE_SD_MMC_CTRLR_H__ */
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@ -1,76 +0,0 @@
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/*
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* Copyright 2011, Marvell Semiconductor Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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* Copyright 2017 Intel Corporation
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*
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* SD host controller specific definitions
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DEVICE_SDHCI_H__
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#define __DEVICE_SDHCI_H__
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#include <device/sd_mmc_ctrlr.h>
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/* Driver specific capabilities */
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#define DRVR_CAP_1V8_VDD 0x00010000
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#define DRVR_CAP_32BIT_DMA_ADDR 0x00020000
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#define DRVR_CAP_BROKEN_R1B 0x00040000
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#define DRVR_CAP_NO_CD 0x00080000
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#define DRVR_CAP_NO_HISPD_BIT 0x00100000
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#define DRVR_CAP_NO_SIMULT_VDD_AND_POWER 0x00200000
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#define DRVR_CAP_REG32_RW 0x00400000
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#define DRVR_CAP_SPI 0x00800000
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#define DRVR_CAP_WAIT_SEND_CMD 0x01000000
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/* ADMA packet descriptor */
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struct sdhci_adma {
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u16 attributes;
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u16 length;
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u32 addr;
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};
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struct sdhci_adma64 {
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u16 attributes;
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u16 length;
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u32 addr;
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u32 addr_hi;
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};
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struct sdhci_ctrlr {
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struct sd_mmc_ctrlr sd_mmc_ctrlr;
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void *ioaddr;
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uint32_t b_max;
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/*
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* Dynamically allocated array of ADMA descriptors to use for data
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* transfers
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*/
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struct sdhci_adma *adma_descs;
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struct sdhci_adma64 *adma64_descs;
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/* Number of ADMA descriptors currently in the array. */
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int adma_desc_count;
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};
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int add_sdhci(struct sdhci_ctrlr *sdhci_ctrlr);
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int sdhci_controller_init(struct sdhci_ctrlr *sdhci_ctrlr, void *ioaddr);
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void sdhci_update_pointers(struct sdhci_ctrlr *sdhci_ctrlr);
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void sdhci_display_setup(struct sdhci_ctrlr *sdhci_ctrlr);
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/* Add SDHCI controller from PCI */
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struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev);
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/* Add SDHCI controller with memory address */
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struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr);
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#endif /* __DEVICE_SDHCI_H__ */
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@ -1,151 +0,0 @@
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/*
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* Copyright 2008,2010 Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Copyright 2013 Google Inc. All rights reserved.
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* Copyright 2017 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DEVICE_STORAGE_H__
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#define __DEVICE_STORAGE_H__
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#include <device/sd_mmc_ctrlr.h>
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_GP_SIZE_MULT_GP0 143 /* RO */
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#define EXT_CSD_GP_SIZE_MULT_GP1 146 /* RO */
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#define EXT_CSD_GP_SIZE_MULT_GP2 149 /* RO */
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#define EXT_CSD_GP_SIZE_MULT_GP3 152 /* RO */
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#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
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#define EXT_CSD_RPMB_SIZE_MULT 168 /* RO */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_PART_CONF 179 /* R/W */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */
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#define EXT_CSD_TRIM_MULT 232 /* RO */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
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#define EXT_CSD_CMD_SET_SECURE (1 << 1)
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#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
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#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
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#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
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#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
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#define EXT_CSD_BUS_WIDTH_STROBE (1<<7) /* Enhanced strobe mode */
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#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
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#define EXT_CSD_TIMING_HS 1 /* High speed */
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#define EXT_CSD_TIMING_HS200 2 /* HS200 */
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#define EXT_CSD_TIMING_HS400 3 /* HS400 */
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#define EXT_CSD_SIZE 512
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/* 179: EXT_CSD_PART_CONF */
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#define EXT_CSD_PART_ACCESS_MASK 7 /* Partition access mask */
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/* 175: EXT_CSD_ERASE_GROUP_DEF */
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#define EXT_CSD_PARTITION_ENABLE 1 /* Enable partition access */
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struct storage_media {
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uint64_t capacity[8]; /* Partition capacity in bytes */
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struct sd_mmc_ctrlr *ctrlr;
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#define MMC_PARTITION_USER 0
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#define MMC_PARTITION_BOOT_1 1
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#define MMC_PARTITION_BOOT_2 2
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#define MMC_PARTITION_RPMB 3
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#define MMC_PARTITION_GP1 4
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#define MMC_PARTITION_GP2 5
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#define MMC_PARTITION_GP3 6
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#define MMC_PARTITION_GP4 7
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uint32_t caps;
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uint32_t version;
|
||||
|
||||
#define SD_VERSION_SD 0x20000
|
||||
#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
|
||||
#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
|
||||
#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
|
||||
#define MMC_VERSION_MMC 0x10000
|
||||
#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
|
||||
#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
|
||||
#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
|
||||
#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
|
||||
#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
|
||||
#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
|
||||
|
||||
uint32_t read_bl_len;
|
||||
uint32_t write_bl_len;
|
||||
int high_capacity;
|
||||
uint32_t tran_speed;
|
||||
/* Erase size in terms of block length. */
|
||||
uint32_t erase_blocks;
|
||||
/* Trim operation multiplier for determining timeout. */
|
||||
uint32_t trim_mult;
|
||||
|
||||
uint32_t ocr;
|
||||
|
||||
#define OCR_BUSY 0x80000000
|
||||
#define OCR_HCS 0x40000000
|
||||
#define OCR_VOLTAGE_MASK 0x00FFFF80
|
||||
#define OCR_ACCESS_MODE 0x60000000
|
||||
|
||||
uint32_t op_cond_response; // The response byte from the last op_cond
|
||||
|
||||
uint32_t scr[2];
|
||||
uint32_t csd[4];
|
||||
uint32_t cid[4];
|
||||
uint16_t rca;
|
||||
|
||||
uint8_t partition_config; /* Duplicate of EXT_CSD_PART_CONF */
|
||||
};
|
||||
|
||||
uint64_t storage_block_erase(struct storage_media *media, uint64_t start,
|
||||
uint64_t count);
|
||||
uint64_t storage_block_fill_write(struct storage_media *media, uint64_t start,
|
||||
uint64_t count, uint32_t fill_pattern);
|
||||
uint64_t storage_block_read(struct storage_media *media, uint64_t start,
|
||||
uint64_t count, void *buffer);
|
||||
uint64_t storage_block_write(struct storage_media *media, uint64_t start,
|
||||
uint64_t count, const void *buffer);
|
||||
|
||||
unsigned int storage_get_current_partition(struct storage_media *media);
|
||||
const char *storage_partition_name(struct storage_media *media,
|
||||
unsigned int partition_number);
|
||||
int storage_setup_media(struct storage_media *media,
|
||||
struct sd_mmc_ctrlr *ctrlr);
|
||||
|
||||
int storage_set_partition(struct storage_media *media,
|
||||
unsigned int partition_number);
|
||||
|
||||
void storage_display_setup(struct storage_media *media);
|
||||
|
||||
#endif /* __DEVICE_STORAGE_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue