From 48c6f66fa42b1c2730df54e13886eee18ed9c0e2 Mon Sep 17 00:00:00 2001
From: "P, Usha" <usha.p@intel.com>
Date: Tue, 8 Jul 2025 23:32:38 +0530
Subject: [PATCH] mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in
 Kconfig

Update TPM related default value for TPM_TIS_ACPI_INTERRUPT based on
schematic_1433518 after mapping GPP_B to GPE0_DW1.

BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I890c6779a24eaa7804594003466e8660af4becc2
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88358
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
---
 src/mainboard/google/ocelot/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig
index 5e8a60b96f..304033b26c 100644
--- a/src/mainboard/google/ocelot/Kconfig
+++ b/src/mainboard/google/ocelot/Kconfig
@@ -142,7 +142,7 @@ config MEMORY_SOLDERDOWN
 
 config TPM_TIS_ACPI_INTERRUPT
 	int
-	default 17 if BOARD_GOOGLE_OCELOT # GPE0_DW0_17 (GPP_B17)
+	default 49 if BOARD_GOOGLE_OCELOT # GPE0_DW1_17 (GPP_B17)
 
 config UART_FOR_CONSOLE
 	int