From 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c Mon Sep 17 00:00:00 2001 From: Deepa Dinamani Date: Tue, 13 May 2014 13:49:42 -0700 Subject: [PATCH] soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc. Define a base address for page table entries. Place it 64KB below the bootblock loading address. BUG=chrome-os-partner:28467 TEST=verified that the page tables are being populated at this address. Also observed that the SPI driver takes 900 ns to process a byte as opposed to 1.5 us in case caching is not enabled. Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7 Signed-off-by: Deepa Dinamani Signed-off-by: Vadim Bendebury Reviewed-on: https://chromium-review.googlesource.com/200332 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 770ad16655..d650349856 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -71,4 +71,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000 +config TTB_BUFFER + hex "memory address for page tables" + default 0x405f0000 + endif