Initial commit of Intel Clearwater 533 (se7501cw2) support
This commit is contained in:
Steven James
parent
1392131143
commit
47994cfb3e
17 changed files with 3578 additions and 0 deletions
296
src/mainboard/intel/Clearwater533/Config
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296
src/mainboard/intel/Clearwater533/Config
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## Set all of the defaults for an x86 architecture
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##
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arch i386
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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##
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## Test for logical cpu thats not BSP
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## This is hyperthreading!
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## it may break!
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##
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#mainboardinit cpu/i786/logical_cpu.inc
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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mainboardinit cpu/i386/reset16.inc USE_FALLBACK_IMAGE
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ldscript cpu/i386/reset16.lds USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset32.inc USE_NORMAL_IMAGE
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ldscript cpu/i386/reset32.lds USE_NORMAL_IMAGE
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript arch/i386/lib/id.lds
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##
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## Startup code for secondary CPUS
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##
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#mainboardinit arch/i386/smp/secondary.inc
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#mainboardinit arch/i386/lib/cpu_reset.inc
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## This is the early phase of linuxBIOS startup
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## Things are delicate and we test to see if we should
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## failover to another image.
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mainboardinit northbridge/intel/E7501/reset_test.inc
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mainboardinit arch/i386/lib/noop_failover.inc USE_NORMAL_IMAGE
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mainboardinit southbridge/intel/82801/cmos_failover.inc USE_FALLBACK_IMAGE
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ldscript mainboard/intel/Clearwater533/failover.lds USE_FALLBACK_IMAGE
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/i786/earlymtrr.inc
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##
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## TESTING!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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##
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mainboardinit mainboard/intel/Clearwater/preserial.inc
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##
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## Setup the serial port
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##
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mainboardinit superio/winbond/w83627hf/setup_serial.inc
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#mainboardinit superio/winbond/w83627hf/setup_led.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit ram/ramtest.inc
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option RAMTEST=1
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#Debug SMJ
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mainboardinit ram/dump_northbridge.inc
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#mainboardinit mainboard/intel/Clearwater/dumpdev.inc
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##
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## Setup RAM
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##
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mainboardinit southbridge/intel/82801ca/smbus.inc
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mainboardinit southbridge/intel/82801ca/smbus_read_block.inc
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mainboardinit southbridge/intel/82801ca/smbus_noop_read_block.inc
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mainboardinit southbridge/intel/82801ca/smbus_read_byte.inc
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#debugging
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mainboardinit sdram/generic_dump_spd.inc USE_FALLBACK_IMAGE
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##
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## Include the secondary Configuration files
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##
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northbridge intel/E7501
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southbridge intel/82801ca
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southbridge intel/82870
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#nsuperio NSC/pc87309 com1={1} com2={1} floppy=1 lpt=1 keyboard=1
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nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1
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dir /src/pc80
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dir /src/superio/winbond/w83627hf
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dir /src/ram/
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cpu p5
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cpu p6
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cpu i786
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##
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## We'll need a udelay function
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##
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option CONFIG_UDELAY_TSC=1
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##
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## Build the objects we have code for in this directory.
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##
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object mainboard.o
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#object mtrr_values.o
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object mptable.o HAVE_MP_TABLE
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object irq_tables.o HAVE_PIRQ_TABLE
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###
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### Build options
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###
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##
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## Location of the DIMM EEPROMS on the SMBUS
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## This is fixed into a narrow range by the DIMM package standard.
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##
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option SMBUS_MEM_CHANNEL_OFF=4
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +2)
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option SMBUS_MEM_DEVICE_INC=1
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##
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## Customize our winbond superio chip for this motherboard
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##
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#option SIO_BASE=0x2e
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#option SIO_SYSTEM_CLK_INPUT=SIO_SYSTEM_CLK_INPUT_48MHZ
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##
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## Build code for the fallback boot
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##
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#option HAVE_FALLBACK_BOOT=1
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##
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## Build code for using cache as RAM
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##
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#option USE_CACHE_RAM=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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##
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## Do not build special code to the keyboard
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##
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option NO_KEYBOARD=1
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option tabe table
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##
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option SMP=1
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option MAX_CPUS=4
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option MAX_PHYSICAL_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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option IOAPIC=1
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##
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## MEMORY_HOLE instructs earlymtrr.inc to
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## enable caching from 0-640KB and to disable
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## caching from 640KB-1MB using fixed MTRRs
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##
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## Enabling this option breaks SMP because secondary
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## CPU identification depends on only variable MTRRs
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## being enabled.
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##
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nooption MEMORY_HOLE
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##
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## Don't do a generic MTRR setup
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## Instead use values from the fixed_mtrr_values array
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##
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#option HAVE_MTRR_TABLE=1
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##
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## Enable both fixed and variable MTRRS
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## When we setup MTRRs in mtrr.c
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##
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## We must setup the fixed mtrrs or we confuse SMP secondary
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## processor identification
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##
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#option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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##
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## Figure out which type of linuxBIOS image to build
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## If we aren't a fallback image we must be a normal image
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## This is useful for optional includes
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##
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option USE_FALLBACK_IMAGE=1
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expr USE_NORMAL_IMAGE=!USE_FALLBACK_IMAGE
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###
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### LinuxBIOS layout values
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###
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE=1048576
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=65536
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00008000
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## For the trick of using cache as ram
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## put the fake ram location at this address
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#option CACHE_RAM_BASE=0xfff70000
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#option CACHE_RAM_SIZE=0x00010000
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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##
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## Use a small 8K heap
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##
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option HEAP_SIZE=0x2000
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER=Clearwater
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option MAINBOARD_VENDOR=Intel
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option PYRO_SERIAL=1
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##
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## Only use the option table in a normal image
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##
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expr USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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expr ROM_SECTION_SIZE =(USE_FALLBACK_IMAGE*65536)+(USE_NORMAL_IMAGE*(ROM_SIZE - 65536))
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expr ROM_SECTION_OFFSET=(USE_FALLBACK_IMAGE*(ROM_SIZE-65536))+(USE_NORMAL_IMAGE*0)
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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#expr ZKERNEL_START =(0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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expr ZKERNEL_START = 0xfff00000 + (USE_NORMAL_IMAGE * 0x10000)
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expr PAYLOAD_SIZE =ROM_SECTION_SIZE - ROM_IMAGE_SIZE
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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#expr _ROMBASE =ZKERNEL_START + PAYLOAD_SIZE
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expr _ROMBASE = 0xffff0000 - (USE_NORMAL_IMAGE*0x10000)
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##
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## Compute a range of ROM that can cached to speed of linuxBIOS,
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## execution speed.
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##
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expr XIP_ROM_SIZE = 65536
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expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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27
src/mainboard/intel/Clearwater533/STATUS
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27
src/mainboard/intel/Clearwater533/STATUS
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@ -0,0 +1,27 @@
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# These are keyword-value pairs.
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# a : separates the keyword from the value
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# the value is arbitrary text delimited by newline.
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# continuation, if needed, will be via the \ at the end of a line
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# comments are indicated by a '#' as the first character.
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# the keywords are case-INSENSITIVE
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owner: Steven James
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email: pyro@linuxlabs.com
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#status: One of unsupported, unstable, stable
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status: unstable
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explanation: Brand new, some memory configs untested
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flash-types: Intel 82802ac8 FWH (8Mbit), 82802ab8 (4Mbit) can be substituted
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payload-types: etherboot, memtest86, pforth (an embedded Forth environment)
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# e.g. linux, plan 9, wince, etc.
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OS-types: linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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OS-issues:
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console-types: serial
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# vga is unsupported, unstable, or stable
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vga: unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 06/02/2003
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Comments:
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Links:
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Mainboard-revision: 0 (pre-production sample)
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# What other mainboards are like this one? List them here.
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AKA:
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40
src/mainboard/intel/Clearwater533/defines
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40
src/mainboard/intel/Clearwater533/defines
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#define S0_WAIT() \
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movw $0x3fd, %dx ;\
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9: inb %dx, %al ;\
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test $0x40, %al ;\
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je 9b
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#define S0_EMIT(char) \
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9: movw $0x3fd, %dx ;\
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inb %dx, %al ;\
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test $0x20, %al ;\
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je 9b ;\
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movb $char,%al ;\
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movw $0x3f8, %dx ;\
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outb %al, %dx
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#define __CONSOLE_INLINE_TX_HEX8(byte) \
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movb byte, %al ; \
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shr $4, %al ; \
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add $'0', %al ; \
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cmp $'9', %al ; \
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jle 9f ; \
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add $39, %al ; \
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9: ; \
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movw $0x3f8, %dx ;\
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outb %al, %dx ;\
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10: movw $0x3fd, %dx ;\
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inb %dx, %al ;\
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test $0x20, %al ;\
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je 10b ;\
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movw $0x3f8, %dx ;\
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mov byte, %al ; \
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and $0x0f, %al ; \
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add $'0', %al ; \
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cmp $'9', %al ; \
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jle 9f ; \
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add $39, %al ; \
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9: ; \
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movw $0x3f8, %dx ;\
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outb %al, %dx
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33
src/mainboard/intel/Clearwater533/example-fallback.config
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33
src/mainboard/intel/Clearwater533/example-fallback.config
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# This will make a target directory of ./clearwater1
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# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
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# CONFIG TOOL. Make it absolute if you like
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target clearwater533-fallback
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# Intel Clearwater (cw2) mainboard
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mainboard intel/Clearwater533
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE=1
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#option CONFIGURE_L2_CACHE=1
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# Use the internal VGA frame buffer device
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#option HAVE_FRAMEBUFFER=1
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option USE_ELF_BOOT=1
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option USE_GENERIC_ROM=1
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option STD_FLASH=1
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option USE_FALLBACK_IMAGE = 1
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option HAVE_PIRQ_TABLE=1
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option DEFAULT_CONSOLE_LOGLEVEL=9
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#payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf
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32
src/mainboard/intel/Clearwater533/example-normal.config
Normal file
32
src/mainboard/intel/Clearwater533/example-normal.config
Normal file
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# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
|
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# CONFIG TOOL. Make it absolute if you like
|
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target clearwater533-primary
|
||||
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||||
# Intel Clearwater (cw2) mainboard
|
||||
mainboard intel/Clearwater533
|
||||
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||||
# Enable Serial Console for debugging
|
||||
# It will come up at 115200,8n1
|
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option SERIAL_CONSOLE=1
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||||
|
||||
# Enable MicroCode update and L2 Cache init for PII and PIII
|
||||
option UPDATE_MICROCODE=1
|
||||
#option CONFIGURE_L2_CACHE=1
|
||||
|
||||
# Use the internal VGA frame buffer device
|
||||
#option HAVE_FRAMEBUFFER=1
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||||
|
||||
option USE_ELF_BOOT=1
|
||||
|
||||
option USE_GENERIC_ROM=1
|
||||
|
||||
option STD_FLASH=1
|
||||
|
||||
option USE_FALLBACK_IMAGE = 0
|
||||
|
||||
option HAVE_PIRQ_TABLE=1
|
||||
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
|
||||
#payload /usr/local/src/LinuxBIOS/etherboot-5.0.6/src/bin32/eepro100.elf
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||||
|
||||
1
src/mainboard/intel/Clearwater533/failover.lds
Normal file
1
src/mainboard/intel/Clearwater533/failover.lds
Normal file
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|
@ -0,0 +1 @@
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__normal_image = 0xf0000 - 8;
|
||||
41
src/mainboard/intel/Clearwater533/irq_tables.c
Normal file
41
src/mainboard/intel/Clearwater533/irq_tables.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
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||||
#include <arch/pirq_routing.h>
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||||
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||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*17, /* there can be total 17 devices on the bus */
|
||||
0, /* Where the interrupt router lies (bus) */
|
||||
0xf8, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0, /* Vendor */
|
||||
0, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xd3, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0x10, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x1,0xe8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x2,0x8, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x2, 0},
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||||
{0x2,0x10, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x3, 0},
|
||||
{0x1,0xf8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x3,0x8, {{0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}, {0x62, 0xdcb8}}, 0x1, 0},
|
||||
{0,0xe8, {{0x60, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xe9, {{0, 0xdef8}, {0x63, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xf0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x8, {{0x61, 0xdcb8}, {0x62, 0xdcb8}, {0x61, 0xdcb8}, {0x62, 0xdcb8}}, 0x4, 0},
|
||||
{0x4,0x10, {{0x63, 0xdcb8}, {0x60, 0xdcb8}, {0x63, 0xdcb8}, {0x60, 0xdcb8}}, 0x5, 0},
|
||||
{0x4,0x18, {{0x69, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x20, {{0x68, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x28, {{0x6b, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x4,0x30, {{0x6a, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xfb, {{0, 0xdef8}, {0x61, 0xdcb8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
}
|
||||
};
|
||||
255
src/mainboard/intel/Clearwater533/mainboard.c
Normal file
255
src/mainboard/intel/Clearwater533/mainboard.c
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
#include <arch/io.h>
|
||||
#include <part/mainboard.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <pci_ids.h>
|
||||
#include <southbridge/intel/82801.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <pc80/isa_dma.h>
|
||||
#include <cpu/i786/multiplier.h>
|
||||
#include <cpu/i786/thermal_monitoring.h>
|
||||
#include <cpu/p6/msr.h>
|
||||
// #include <superio/w83627hf.h>
|
||||
#include <superio/generic.h>
|
||||
#include <subr.h>
|
||||
#include <smbus.h>
|
||||
#include <ramtest.h>
|
||||
// #include <northbridge/intel/82860/rdram.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
|
||||
#define SMBUS_MEM_DEVICE_0 (0xa << 3)
|
||||
extern int rdram_chips; /* number of ram chips on the rimms */
|
||||
|
||||
|
||||
unsigned long initial_apicid[MAX_CPUS] =
|
||||
{
|
||||
0, 6, 1, 7
|
||||
};
|
||||
|
||||
#ifndef CPU_CLOCK_MULTIPLIER
|
||||
#define CPU_CLOCK_MULTIPLIER XEON_X17
|
||||
#endif
|
||||
|
||||
#define MAINBOARD_POWER_ON 1
|
||||
#define MAINBOARD_POWER_OFF 2
|
||||
|
||||
#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
void dump_pci_dev(int bus, int dev, int fn)
|
||||
{
|
||||
|
||||
unsigned int offset = 0x80000000;
|
||||
unsigned int i;
|
||||
unsigned short devfn;
|
||||
unsigned char byte;
|
||||
|
||||
devfn = (dev <<3) | fn;
|
||||
offset |= (bus << 16) | (devfn << 8);
|
||||
|
||||
printk_notice("dump %u:%u.%u:\n", bus,dev,fn);
|
||||
|
||||
for(i=0; i<256; i++) {
|
||||
|
||||
if(! (i & 0x0f))
|
||||
printk_notice( "\n%02x: ", i);
|
||||
|
||||
pcibios_read_config_byte(bus, devfn, i, &byte);
|
||||
printk_notice( "%02x ", byte);
|
||||
}
|
||||
|
||||
printk_notice("\nDone.\n\n");
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static void set_power_on_after_power_fail(int setting)
|
||||
{
|
||||
switch(setting) {
|
||||
case MAINBOARD_POWER_ON:
|
||||
default:
|
||||
ich3_power_after_power_fail(1);
|
||||
// w832627hf_power_after_power_fail(POWER_ON);
|
||||
break;
|
||||
case MAINBOARD_POWER_OFF:
|
||||
ich3_power_after_power_fail(0);
|
||||
// w832627hf_power_after_power_fail(POWER_OFF);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void set_thermal_monitoring(int thermal_monitoring)
|
||||
{
|
||||
int tm_high,tm_low;
|
||||
|
||||
rdmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
if(thermal_monitoring != THERMAL_MONITORING_OFF) {
|
||||
tm_low |= THERMAL_MONITORING_SET;
|
||||
}
|
||||
else {
|
||||
tm_low &= ~THERMAL_MONITORING_SET;
|
||||
}
|
||||
wrmsr(MISC_ENABLE,tm_low,tm_high);
|
||||
return;
|
||||
}
|
||||
|
||||
void mainboard_fixup(void)
|
||||
{
|
||||
int cpu_clock_multiplier;
|
||||
int power_on_after_power_fail;
|
||||
int thermal_monitoring;
|
||||
|
||||
printk_notice("CW2 mainboard fixup:\n");
|
||||
ich3_enable_ioapic();
|
||||
p64h2_enable_ioapic();
|
||||
ich3_enable_serial_irqs();
|
||||
ich3_enable_ide(1,1);
|
||||
// test, SMJ
|
||||
// ich3_rtc_init();
|
||||
ich3_lpc_route_dma(0xff);
|
||||
isa_dma_init();
|
||||
ich3_1e0_misc();
|
||||
ich3_1f0_misc();
|
||||
|
||||
// SMJ dump some registers!
|
||||
#if 0
|
||||
dump_pci_dev(0, 0, 0);
|
||||
|
||||
printk_notice("1st bridge:\n");
|
||||
dump_pci_dev(0, 3, 0);
|
||||
|
||||
|
||||
printk_notice("APIC:\n");
|
||||
dump_pci_dev(1, 0x1c, 0);
|
||||
dump_pci_dev(1, 0x1e, 0);
|
||||
|
||||
printk_notice("bridge:\n");
|
||||
dump_pci_dev(1, 0x1d, 0);
|
||||
dump_pci_dev(1, 0x1f, 0);
|
||||
|
||||
printk_notice("ether (connected to 1:0x1f.0):\n");
|
||||
dump_pci_dev(3, 0x7, 0);
|
||||
dump_pci_dev(3, 0x7, 1);
|
||||
#endif
|
||||
|
||||
// test only SMJ
|
||||
return;
|
||||
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
if(get_option(&cpu_clock_multiplier, "CPU_clock_speed"))
|
||||
cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER;
|
||||
ich3_set_cpu_multiplier(cpu_clock_multiplier);
|
||||
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
if(get_option(&power_on_after_power_fail, "power_on_after_power_fail"))
|
||||
power_on_after_power_fail = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
|
||||
set_power_on_after_power_fail(power_on_after_power_fail);
|
||||
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
if(get_option(&thermal_monitoring, "thermal_monitoring"))
|
||||
thermal_monitoring = THERMAL_MONITORING_OFF;
|
||||
set_thermal_monitoring(thermal_monitoring);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
ich3_hard_reset();
|
||||
}
|
||||
|
||||
#ifdef USE_CACHE_RAM
|
||||
|
||||
void cache_ram_start(void)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = 0;
|
||||
/* displayinit MUST PRECEDE ALL PRINTK! */
|
||||
|
||||
#if 1
|
||||
displayinit();
|
||||
#endif
|
||||
printk_info("Finding PCI configuration type.\n");
|
||||
pci_set_method();
|
||||
printk_info("Setting up smbus controller\n");
|
||||
smbus_setup();
|
||||
ich3_rtc_init();
|
||||
printk_info("Selecting rdram i2c bus\n");
|
||||
// select_rdram_i2c();
|
||||
|
||||
#if 0
|
||||
display_smbus_spd();
|
||||
#endif
|
||||
|
||||
init_memory();
|
||||
|
||||
#if 0
|
||||
{
|
||||
unsigned long addr;
|
||||
for(addr = 0; addr < 0x20000000; addr += 0x02000000) {
|
||||
ram_fill(addr, addr + 0x400);
|
||||
}
|
||||
/* Do some dummy writes to flush a write cache, in the
|
||||
* processor.
|
||||
*/
|
||||
ram_fill(0xc0000000, 0xc0000400);
|
||||
for(addr = 0; addr < 0x20000000; addr += 0x02000000) {
|
||||
ram_verify(addr, addr + 0x400, 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if 1
|
||||
printk_debug("starting ramcheck\n");
|
||||
error |= ramcheck(0x00000000, 0x00080000, 40);
|
||||
error |= ramcheck(0x02000000, 0x02080000, 40);
|
||||
error |= ramcheck(0x04000000, 0x04080000, 40);
|
||||
error |= ramcheck(0x06000000, 0x06080000, 40);
|
||||
error |= ramcheck(0x08000000, 0x08080000, 40);
|
||||
error |= ramcheck(0x0a000000, 0x0a080000, 40);
|
||||
error |= ramcheck(0x0c000000, 0x0c080000, 40);
|
||||
error |= ramcheck(0x0e000000, 0x0e080000, 40);
|
||||
error |= ramcheck(0x1a000000, 0x1a080000, 40);
|
||||
#if 0
|
||||
error |= ramcheck(0x10000000, 0x10080000, 20);
|
||||
error |= ramcheck(0x12000000, 0x12080000, 20);
|
||||
error |= ramcheck(0x14000000, 0x14080000, 20);
|
||||
error |= ramcheck(0x16000000, 0x16080000, 20);
|
||||
error |= ramcheck(0x18000000, 0x18080000, 20);
|
||||
error |= ramcheck(0x1a000000, 0x1a080000, 20);
|
||||
error |= ramcheck(0x1c000000, 0x1c080000, 20);
|
||||
error |= ramcheck(0x1e000000, 0x1e080000, 20);
|
||||
#endif
|
||||
#endif
|
||||
#if 0
|
||||
error |= ramcheck(0x00000000, 0x00080000, 20);
|
||||
#endif
|
||||
#if 0
|
||||
display_rdram_regs(rdram_chips );
|
||||
#endif
|
||||
#if 0
|
||||
display_mch_regs();
|
||||
#endif
|
||||
if (error) {
|
||||
printk_err("Something isn't working!!!\n");
|
||||
while(1);
|
||||
} else {
|
||||
printk_info("Leaving cacheram...\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
161
src/mainboard/intel/Clearwater533/mptable.c
Normal file
161
src/mainboard/intel/Clearwater533/mptable.c
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
/* generatred by MPTable, version 2.0.15*/
|
||||
/* as modified by RGM for LinuxBIOS */
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <string.h>
|
||||
#include <printk.h>
|
||||
#include <pci.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "LnxLabs ";
|
||||
static const char productid[12] = "7501CW2 ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
#if 0
|
||||
smp_write_processor(mc, 0x00, 0x14, CPU_BOOTPROCESSOR | CPU_ENABLED,
|
||||
0x00000f24, 0x3febfbff);
|
||||
smp_write_processor(mc, 0x06, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff);
|
||||
smp_write_processor(mc, 0x01, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff);
|
||||
smp_write_processor(mc, 0x07, 0x14, CPU_ENABLED, 0x00000f24, 0x3febfbff);
|
||||
#else
|
||||
smp_write_processors(mc, processor_map);
|
||||
#endif
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "PCI ");
|
||||
smp_write_bus(mc, 4, "PCI ");
|
||||
smp_write_bus(mc, 5, "ISA ");
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 4, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 5, 0x20, base);
|
||||
}
|
||||
dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));
|
||||
if (dev) {
|
||||
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 8, 0x20, base);
|
||||
}
|
||||
}
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x9, 0x2, 0x9);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0xc, 0x2, 0x15);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x14);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x18, 0x2, 0x16);
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* MP Config Extended Table Entries:
|
||||
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: I/O address
|
||||
address base: 0x0
|
||||
address range: 0x10000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0x40000000
|
||||
address range: 0xbee00000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 0 address type: memory address
|
||||
address base: 0xfee01000
|
||||
address range: 0x11ff000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 4 address type: memory address
|
||||
address base: 0xa0000
|
||||
address range: 0x20000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 4 address type: memory address
|
||||
address base: 0xcc000
|
||||
address range: 0x10000
|
||||
--
|
||||
System Address Space
|
||||
bus ID: 4 address type: memory address
|
||||
address base: 0xe0000
|
||||
address range: 0x4000
|
||||
--
|
||||
Bus Heirarchy
|
||||
bus ID: 5 bus info: 0x01 parent bus ID: 0--
|
||||
Compatibility Bus Address
|
||||
bus ID: 0 address modifier: add
|
||||
predefined range: 0x00000000--
|
||||
Compatibility Bus Address
|
||||
bus ID: 0 address modifier: add
|
||||
predefined range: 0x00000001 There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p
|
||||
",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
49
src/mainboard/intel/Clearwater533/mtrr_values.c
Normal file
49
src/mainboard/intel/Clearwater533/mtrr_values.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
#include <cpu/p6/mtrr.h>
|
||||
|
||||
/* We want to cache memory as efficiently as possible.
|
||||
*/
|
||||
#define RAM MTRR_TYPE_WRBACK
|
||||
/* We can't use Write Combining on a legacy frame buffer because
|
||||
* it is incompatible with EGA 16 color video modes...
|
||||
*/
|
||||
#define FB MTRR_TYPE_UNCACHABLE
|
||||
/* For areas that are supposed to cover roms it makes no
|
||||
* sense to cache writes.
|
||||
*/
|
||||
#define ROM MTRR_TYPE_WRPROT
|
||||
|
||||
|
||||
unsigned char fixed_mtrr_values[][4] = {
|
||||
/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */
|
||||
{FB, FB, FB, FB}, {FB, FB, FB, FB},
|
||||
|
||||
/* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
|
||||
/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
|
||||
{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
|
||||
};
|
||||
458
src/mainboard/intel/Clearwater533/preserial.inc
Normal file
458
src/mainboard/intel/Clearwater533/preserial.inc
Normal file
|
|
@ -0,0 +1,458 @@
|
|||
jmp preserial
|
||||
|
||||
|
||||
#define S0_WAIT() \
|
||||
movw $0x3fd, %dx ;\
|
||||
9: inb %dx, %al ;\
|
||||
test $0x40, %al ;\
|
||||
je 9b
|
||||
|
||||
#define S0_EMIT(char) \
|
||||
9: movw $0x3fd, %dx ;\
|
||||
inb %dx, %al ;\
|
||||
test $0x20, %al ;\
|
||||
je 9b ;\
|
||||
movb $char,%al ;\
|
||||
movw $0x3f8, %dx ;\
|
||||
outb %al, %dx
|
||||
|
||||
#define __CONSOLE_INLINE_TX_HEX8(byte) \
|
||||
movb byte, %al ; \
|
||||
shr $4, %al ; \
|
||||
add $'0', %al ; \
|
||||
cmp $'9', %al ; \
|
||||
jle 9f ; \
|
||||
add $39, %al ; \
|
||||
9: ; \
|
||||
movw $0x3f8, %dx ;\
|
||||
outb %al, %dx ;\
|
||||
10: movw $0x3fd, %dx ;\
|
||||
inb %dx, %al ;\
|
||||
test $0x20, %al ;\
|
||||
je 10b ;\
|
||||
movw $0x3f8, %dx ;\
|
||||
mov byte, %al ; \
|
||||
and $0x0f, %al ; \
|
||||
add $'0', %al ; \
|
||||
cmp $'9', %al ; \
|
||||
jle 9f ; \
|
||||
add $39, %al ; \
|
||||
9: ; \
|
||||
movw $0x3f8, %dx ;\
|
||||
outb %al, %dx
|
||||
|
||||
southbridge_table_start:
|
||||
|
||||
.byte 0x01, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00 # 40
|
||||
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00 # 50
|
||||
.byte 0x0a, 0x0b, 0x80, 0x09, 0xd1, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00 # 60
|
||||
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # 70
|
||||
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # 80
|
||||
.byte 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # 90
|
||||
.byte 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # a0
|
||||
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # b0
|
||||
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # c0
|
||||
.byte 0x86, 0x39, 0x00, 0x00, 0x02, 0x0f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 # d0
|
||||
.byte 0x10, 0x00, 0x00, 0xc0, 0x00, 0xa0, 0x0f, 0x1c, 0x33, 0x22, 0x11, 0x00, 0x00, 0x00, 0x67, 0x45 # e0
|
||||
.byte 0x0f, 0x00, 0x60, 0x84, 0x00, 0x00, 0x00, 0x00, 0x47, 0x0f, 0x0e, 0x00, 0x00, 0x00, 0x81, 0x00 # f0
|
||||
|
||||
southbridge_end:
|
||||
|
||||
.globl preserial
|
||||
preserial:
|
||||
|
||||
.code32
|
||||
|
||||
cli
|
||||
|
||||
#call off the dog
|
||||
movw $0x461, %dx
|
||||
movb $0x20, %al
|
||||
outb %al, %dx
|
||||
dec %dx
|
||||
movb $0x01, %al
|
||||
outb %al, %dx
|
||||
|
||||
movl $0x8000f8d4, %eax
|
||||
movw $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
movw $0xcfc, %dx
|
||||
movb $0x2, %al
|
||||
# movb $0x0, %al # 0x02 here to disable watchdog function
|
||||
outb %al, %dx
|
||||
|
||||
# movw $0x468, %dx
|
||||
# movw $0x800, %ax
|
||||
# outw %ax, %dx
|
||||
#
|
||||
|
||||
#turn on LPC I/o access to superio
|
||||
movl $0x8000f8e6, %eax
|
||||
mov $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
|
||||
mov $0xcfc, %dx
|
||||
movw $0x1c0f, %ax
|
||||
outw %ax, %dx
|
||||
|
||||
#assign i/o ranges for serial I/O
|
||||
movl $0x8000f8e0, %eax
|
||||
mov $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
|
||||
mov $0xcfc, %dx
|
||||
mov $0x10, %al
|
||||
outb %al, %dx
|
||||
|
||||
#attempt to get Natsemi superio to ID itself
|
||||
#movw $0x2e, %dx
|
||||
#movb $0x20, %al
|
||||
#outb %al, %dx
|
||||
|
||||
#inc %dx
|
||||
#inb %dx, %al
|
||||
|
||||
#cmp $0x0ee, %al
|
||||
#je corrupt_cmos
|
||||
|
||||
#OK, now, lets turn serial on!
|
||||
|
||||
jmp noreset
|
||||
#first, reset the serial chip to defaults
|
||||
movw $0x2e, %dx
|
||||
movb $0x21, %al
|
||||
outb %al, %dx
|
||||
|
||||
inc %dx
|
||||
movb $0x13, %al
|
||||
outb %al, %dx
|
||||
|
||||
noreset:
|
||||
movw $0x2e, %dx
|
||||
movb $0x21, %al
|
||||
outb %al, %dx
|
||||
|
||||
inc %dx
|
||||
movb $0x19, %al
|
||||
outb %al, %dx
|
||||
|
||||
dec %dx
|
||||
movb $0x22, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
outb %al, %dx # YES! 22->22
|
||||
|
||||
dec %dx
|
||||
movb $0x23, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
movb $0x72, %al
|
||||
outb %al, %dx
|
||||
|
||||
dec %dx
|
||||
movb $0x24, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
movb $0x26, %al
|
||||
outb %al, %dx
|
||||
|
||||
dec %dx
|
||||
movb $0x2a, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
movb $0x0b, %al
|
||||
outb %al, %dx
|
||||
|
||||
#enable serial
|
||||
dec %dx
|
||||
movb $0x07, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
movb $0x03, %al
|
||||
outb %al, %dx
|
||||
|
||||
dec %dx
|
||||
movb $0x30, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
movb $0x01, %al
|
||||
outb %al, %dx
|
||||
|
||||
#O.K. now lets try to set up serial part way, then confirm that its active
|
||||
|
||||
#turn off serial interrupts, we have no vectors
|
||||
movw $0x3f9, %dx
|
||||
movb $0x0, %al
|
||||
outb %al, %dx
|
||||
|
||||
#set divisor to 115200
|
||||
movw $0x3fb, %dx
|
||||
movb $0x83, %al
|
||||
outb %al, %dx
|
||||
|
||||
movw $0x3f8, %dx
|
||||
movb $0x01, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
|
||||
movb $0x00, %al
|
||||
outb %al, %dx
|
||||
|
||||
#set n81
|
||||
movw $0x3fb, %dx
|
||||
movb $0x03, %al
|
||||
outb %al, %dx
|
||||
|
||||
#FIFO setup $0xc7 -> 0x3fa
|
||||
movw $0x3fa, %dx
|
||||
movb $0xc7, %al
|
||||
out %al, %dx
|
||||
|
||||
|
||||
|
||||
#set DTR, RTS, OUT2 (whatever that is)
|
||||
movw $0x3fc, %dx
|
||||
movb $0xb, %al
|
||||
outb %al, %dx
|
||||
|
||||
jmp preserial_out
|
||||
|
||||
#set null descriptor to all but CS
|
||||
#movw $0x0, %ax
|
||||
#movw %ax, %ds
|
||||
#movw %ax, %es
|
||||
#movw %ax, %fs
|
||||
#movw %ax, %gs
|
||||
|
||||
S0_EMIT('C')
|
||||
S0_EMIT('S')
|
||||
S0_EMIT(':')
|
||||
movw %cs, %ax
|
||||
movw %ax, %bx
|
||||
__CONSOLE_INLINE_TX_HEX8(%bh)
|
||||
__CONSOLE_INLINE_TX_HEX8(%bl)
|
||||
S0_EMIT('\r')
|
||||
S0_EMIT('\n')
|
||||
|
||||
S0_EMIT('D')
|
||||
S0_EMIT('S')
|
||||
S0_EMIT(':')
|
||||
S0_WAIT()
|
||||
movw %ds, %ax
|
||||
movw %ax, %bx
|
||||
__CONSOLE_INLINE_TX_HEX8(%bh)
|
||||
__CONSOLE_INLINE_TX_HEX8(%bl)
|
||||
S0_EMIT('\r')
|
||||
S0_EMIT('\n')
|
||||
|
||||
S0_EMIT('C')
|
||||
S0_EMIT('R')
|
||||
S0_EMIT('0')
|
||||
S0_EMIT(':')
|
||||
|
||||
S0_WAIT()
|
||||
|
||||
movl %cr0, %eax
|
||||
movl %eax, %ebx
|
||||
movl %eax, %ecx
|
||||
shr $0x16, %ebx
|
||||
|
||||
__CONSOLE_INLINE_TX_HEX8(%bh)
|
||||
__CONSOLE_INLINE_TX_HEX8(%bl)
|
||||
movw %cx,%bx
|
||||
|
||||
__CONSOLE_INLINE_TX_HEX8(%bh)
|
||||
__CONSOLE_INLINE_TX_HEX8(%bl)
|
||||
|
||||
S0_EMIT('\r')
|
||||
S0_EMIT('\n')
|
||||
|
||||
movl $0x10002, %esi
|
||||
#sgdt %cs:(%esi)
|
||||
sgdt (%esi)
|
||||
|
||||
S0_EMIT('G')
|
||||
S0_EMIT('D')
|
||||
S0_EMIT('T')
|
||||
S0_EMIT(':')
|
||||
|
||||
movw (0x10002), %cx
|
||||
movl (0x10004), %ebx
|
||||
|
||||
out1:
|
||||
__CONSOLE_INLINE_TX_HEX8( %cs:(%ebx) )
|
||||
inc %bx
|
||||
dec %cx
|
||||
jnz out1
|
||||
|
||||
#movw $0x4, %cx
|
||||
#loop3:
|
||||
#__CONSOLE_INLINE_TX_HEX8(%bl)
|
||||
#shr $0x08, %ebx
|
||||
#dec %cx
|
||||
#jnz loop3
|
||||
|
||||
|
||||
#just a test, emit a PYRO
|
||||
S0_EMIT('P')
|
||||
|
||||
jmp dolgdt
|
||||
|
||||
.align 4
|
||||
dolgdt:
|
||||
lgdt %cs:gdtptr
|
||||
S0_EMIT('Y')
|
||||
ljmp $0x10,$csload
|
||||
csload:
|
||||
S0_EMIT('R')
|
||||
|
||||
movw $0x18, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %fs
|
||||
movw %ax, %gs
|
||||
movw %ax, %ss
|
||||
|
||||
S0_EMIT('O')
|
||||
S0_EMIT('\r')
|
||||
S0_EMIT('\n')
|
||||
|
||||
#movb $0x50, %al
|
||||
#movw $0x3f8, %dx
|
||||
#outb %al, %dx
|
||||
#movb $0x59, %al
|
||||
#outb %al, %dx
|
||||
#movb $0x52, %al
|
||||
#outb %al, %dx
|
||||
#movb $0x4f, %al
|
||||
#outb %al, %dx
|
||||
|
||||
#movb $0x0d, %al
|
||||
#outb %al, %dx
|
||||
|
||||
#movb $0x0a, %al
|
||||
#outb %al, %dx
|
||||
|
||||
|
||||
#indicate we did it by clearing DTR
|
||||
movw $0x3fc, %dx
|
||||
movb $0x0a, %al
|
||||
outb %al, %dx
|
||||
|
||||
|
||||
|
||||
jmp preserial_out
|
||||
|
||||
movl $southbridge_table_start, %esi
|
||||
movl $(southbridge_end - southbridge_table_start), %ecx
|
||||
shrl $0x02, %ecx
|
||||
movl $0x8000f840, %eax
|
||||
movl %eax, %ebx
|
||||
|
||||
next_dword:
|
||||
movw $0xcf8, %dx
|
||||
movl %ebx, %eax
|
||||
outl %eax, %dx
|
||||
inc %eax
|
||||
inc %eax
|
||||
inc %eax
|
||||
inc %eax
|
||||
movl %eax, %ebx
|
||||
lodsl (%esi), %eax
|
||||
movw $0xcfc, %dx
|
||||
outl %eax, %dx
|
||||
loopnz next_dword
|
||||
|
||||
|
||||
jmp preserial_out
|
||||
|
||||
|
||||
movl $0x8000f8e0, %eax
|
||||
mov $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
|
||||
mov $0xcfc, %dx
|
||||
mov $0x10, %al
|
||||
outb %al, %dx
|
||||
|
||||
|
||||
|
||||
jmp preserial_out
|
||||
|
||||
corrupt_cmos:
|
||||
mov $0x72, %dx
|
||||
mov $0x50, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
mov $0x42, %al
|
||||
outb %al, %dx
|
||||
|
||||
dec %dx
|
||||
mov $0x51, %al
|
||||
outb %al, %dx
|
||||
inc %dx
|
||||
mov $0xbe, %al
|
||||
outb %al, %dx
|
||||
|
||||
|
||||
#now, strobe HD light a few times to prove we made it here
|
||||
|
||||
mov $30, %bx
|
||||
mov $0x480, %dx
|
||||
again:
|
||||
mov $0xa7, %al
|
||||
outb %al, %dx
|
||||
movl $0xfffffff,%ecx
|
||||
loop1:
|
||||
dec %ecx
|
||||
jnz loop1
|
||||
|
||||
mov $0xa6, %al
|
||||
outb %al, %dx
|
||||
movl $0xfffffff,%ecx
|
||||
loop2:
|
||||
dec %ecx
|
||||
jnz loop2
|
||||
|
||||
|
||||
dec %bx
|
||||
jnz again
|
||||
|
||||
|
||||
preserial_out:
|
||||
|
||||
S0_EMIT('A')
|
||||
S0_EMIT('P')
|
||||
S0_EMIT('I')
|
||||
S0_EMIT('C')
|
||||
S0_EMIT('I')
|
||||
S0_EMIT('D')
|
||||
S0_EMIT(':')
|
||||
|
||||
movl $APIC_DEFAULT_BASE, %edi
|
||||
movl APIC_ID(%edi), %eax
|
||||
shrl $24, %eax
|
||||
|
||||
__CONSOLE_INLINE_TX_HEX8(%al)
|
||||
S0_EMIT('\r')
|
||||
S0_EMIT('\n')
|
||||
|
||||
|
||||
#very temporary, set TOLM to 1 Gig. This should be enumerated or otherwise tested!
|
||||
movl $0x800000c4, %eax
|
||||
movw $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
movw $0x4000, %ax
|
||||
movw $0xcfc, %dx
|
||||
outw %ax, %dx
|
||||
|
||||
#set PCI dev 0:0.0.e0 < 0x1e
|
||||
movl $0x800000e0, %eax
|
||||
movw $0xcf8, %dx
|
||||
outl %eax, %dx
|
||||
movb $0x1e, %al
|
||||
movw $0xcfc, %dx
|
||||
outb %al, %dx
|
||||
|
||||
jmp console0
|
||||
|
||||
10
src/northbridge/intel/E7501/Config
Normal file
10
src/northbridge/intel/E7501/Config
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#mainboardinit cpu/i786/enable_sse.inc
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit ram/spotcheck.inc
|
||||
mainboardinit northbridge/intel/E7501/raminit.inc
|
||||
mainboardinit northbridge/intel/E7501/sdram_enable.inc
|
||||
mainboardinit sdram/generic_sdram.inc
|
||||
#mainboardinit cpu/i786/disable_sse.inc
|
||||
mainboardinit sdram/generic_cache_linuxbios.inc
|
||||
|
||||
object northbridge.o
|
||||
103
src/northbridge/intel/E7501/northbridge.c
Normal file
103
src/northbridge/intel/E7501/northbridge.c
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
#include <mem.h>
|
||||
#include <pci.h>
|
||||
#include <arch/io.h>
|
||||
#include <part/sizeram.h>
|
||||
#include <printk.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
|
||||
struct mem_range *sizeram(void)
|
||||
{
|
||||
static struct mem_range mem[4];
|
||||
/* the units of tolm are 64 KB */
|
||||
/* the units of drb16 are 64 MB */
|
||||
uint16_t tolm, remapbase, remaplimit, drb16;
|
||||
uint16_t tolm_r, remapbase_r, remaplimit_r;
|
||||
uint8_t drb;
|
||||
int remap_high;
|
||||
|
||||
/* Calculate and report the top of low memory and
|
||||
* any remapping.
|
||||
*/
|
||||
/* Test if the remap memory high option is set */
|
||||
remap_high = 0;
|
||||
if(get_option(&remap_high, "remap_memory_high")){
|
||||
remap_high = 0;
|
||||
}
|
||||
printk_debug("remap_high is %d\n", remap_high);
|
||||
/* get out the value of the highest DRB. This tells the end of
|
||||
* physical memory. The units are ticks of 64 MB i.e. 1 means
|
||||
* 64 MB.
|
||||
*/
|
||||
pcibios_read_config_byte(0, 0, 0x67, &drb);
|
||||
drb16 = (uint16_t)drb;
|
||||
if(remap_high && (drb16 > 0x08)) {
|
||||
/* We only come here if we have at least 512MB of memory,
|
||||
* so it is safe to hard code tolm.
|
||||
* 0x2000 means 512MB
|
||||
*/
|
||||
|
||||
tolm = 0x2000;
|
||||
/* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
|
||||
if(drb16 > 0x0040) {
|
||||
/* There is more than 4GB of memory put
|
||||
* the remap window at the end of ram.
|
||||
*/
|
||||
remapbase = drb16;
|
||||
remaplimit = remapbase + 0x38;
|
||||
}
|
||||
else {
|
||||
remapbase = 0x0040;
|
||||
remaplimit = remapbase + (drb16-8);
|
||||
}
|
||||
}
|
||||
else {
|
||||
tolm = (uint16_t)((pci_memory_base >> 16)&0x0f800);
|
||||
if((tolm>>8) >= (drb16<<2)) {
|
||||
tolm = (drb16<<10);
|
||||
remapbase = 0x3ff;
|
||||
remaplimit = 0;
|
||||
}
|
||||
else {
|
||||
remapbase = drb16;
|
||||
remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
|
||||
}
|
||||
}
|
||||
/* Write the ram configruation registers,
|
||||
* preserving the reserved bits.
|
||||
*/
|
||||
pcibios_read_config_word(0, 0, 0xc4, &tolm_r);
|
||||
tolm |= (tolm_r & 0x7ff);
|
||||
pcibios_write_config_word(0, 0, 0xc4, tolm);
|
||||
pcibios_read_config_word(0, 0, 0xc6, &remapbase_r);
|
||||
remapbase |= (remapbase_r & 0xfc00);
|
||||
pcibios_write_config_word(0, 0, 0xc6, remapbase);
|
||||
pcibios_read_config_word(0, 0, 0xc8, &remaplimit_r);
|
||||
remaplimit |= (remaplimit_r & 0xfc00);
|
||||
pcibios_write_config_word(0, 0, 0xc8, remaplimit);
|
||||
|
||||
#if 0
|
||||
printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
|
||||
#endif
|
||||
|
||||
mem[0].basek = 0;
|
||||
mem[0].sizek = 640;
|
||||
mem[1].basek = 768;
|
||||
/* Convert size in 64K bytes to size in K bytes */
|
||||
mem[1].sizek = (tolm << 6) - mem[1].basek;
|
||||
mem[2].basek = 0;
|
||||
mem[2].sizek = 0;
|
||||
if ((drb << 16) > (tolm << 6)) {
|
||||
/* We don't need to consider the remap window
|
||||
* here because we put it immediately after the
|
||||
* rest of ram.
|
||||
* All we must do is calculate the amount
|
||||
* of unused memory and report it at 4GB.
|
||||
*/
|
||||
mem[2].basek = 4096*1024;
|
||||
mem[2].sizek = (drb << 16) - (tolm << 6);
|
||||
}
|
||||
mem[3].basek = 0;
|
||||
mem[3].sizek = 0;
|
||||
|
||||
return mem;
|
||||
}
|
||||
1922
src/northbridge/intel/E7501/raminit.inc
Normal file
1922
src/northbridge/intel/E7501/raminit.inc
Normal file
File diff suppressed because it is too large
Load diff
10
src/northbridge/intel/E7501/reset_test.inc
Normal file
10
src/northbridge/intel/E7501/reset_test.inc
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#define MCH_DRC 0x7c
|
||||
#define DRC_DONE (1 << 29)
|
||||
/* If I have already booted once skip a bunch of initialization */
|
||||
/* To see if I have already booted I check to see if memory
|
||||
* has been enabled.
|
||||
*/
|
||||
movl $MCH_DRC, %eax
|
||||
PCI_READ_CONFIG_DWORD
|
||||
testl $DRC_DONE, %eax
|
||||
setnz %al
|
||||
132
src/northbridge/intel/E7501/sdram_enable.inc
Normal file
132
src/northbridge/intel/E7501/sdram_enable.inc
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
jmp sdram_enable_out
|
||||
|
||||
#ifndef RAM_NOP
|
||||
#error RAM_NOP not defined
|
||||
#endif
|
||||
|
||||
#ifndef RAM_PRECHARGE
|
||||
#error RAM_PRECHARGE not defined
|
||||
#endif
|
||||
|
||||
#ifndef RAM_EMRS
|
||||
#error RAM_EMRS not defined
|
||||
#endif
|
||||
|
||||
#ifndef RAM_MRS
|
||||
#error RAM_MRS not defined
|
||||
#endif
|
||||
|
||||
#ifndef RAM_CBR
|
||||
#error RAM_CBR not defined
|
||||
#endif
|
||||
|
||||
#ifndef RAM_NORMAL
|
||||
#error RAM_NORMAL not defined
|
||||
#endif
|
||||
|
||||
#if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
|
||||
ram_enable_1: .string "Ram Enable 1\r\n"
|
||||
ram_enable_2: .string "Ram Enable 2\r\n"
|
||||
ram_enable_3: .string "Ram Enable 3\r\n"
|
||||
ram_enable_4: .string "Ram Enable 4\r\n"
|
||||
ram_enable_5: .string "Ram Enable 5\r\n"
|
||||
ram_enable_6: .string "Ram Enable 6\r\n"
|
||||
ram_enable_7: .string "Ram Enable 7\r\n"
|
||||
ram_enable_8: .string "Ram Enable 8\r\n"
|
||||
ram_enable_9: .string "Ram Enable 9\r\n"
|
||||
ram_enable_10: .string "Ram Enable 10\r\n"
|
||||
ram_enable_11: .string "Ram Enable 11\r\n"
|
||||
#endif
|
||||
|
||||
/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
|
||||
/* delay for 200us */
|
||||
|
||||
#define DO_DELAY \
|
||||
movl $16, %edi ; \
|
||||
1: SLOW_DOWN_IO ; \
|
||||
decl %edi ; \
|
||||
jnz 1b
|
||||
|
||||
|
||||
#define EXTRA_DELAY DO_DELAY
|
||||
|
||||
enable_sdram:
|
||||
/* 1 & 2 Power up and start clocks */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_1)
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_2)
|
||||
|
||||
/* A 200us delay is needed */
|
||||
|
||||
DO_DELAY
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 3. Apply NOP */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_3)
|
||||
RAM_NOP()
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 4 Precharge all */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_4)
|
||||
RAM_PRECHARGE()
|
||||
EXTRA_DELAY
|
||||
|
||||
/* wait until the all banks idle state... */
|
||||
/* 5. Issue EMRS to enable DLL */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_5)
|
||||
RAM_EMRS()
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 6. Reset DLL */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_6)
|
||||
RAM_MRS(1)
|
||||
EXTRA_DELAY
|
||||
|
||||
/* Ensure a 200us delay between the DLL reset in step 6 and the final
|
||||
* mode register set in step 9.
|
||||
* Infineon needs this before any other command is sent to the ram.
|
||||
*/
|
||||
DO_DELAY
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 7 Precharge all */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_7)
|
||||
RAM_PRECHARGE()
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_8)
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
/* And for good luck 6 more CBRs */
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
RAM_CBR()
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 9 mode register set */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_9)
|
||||
RAM_MRS(0)
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 10 DDR Receive FIFO RE-Sync */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_10)
|
||||
RAM_RESET_DDR_PTR()
|
||||
EXTRA_DELAY
|
||||
|
||||
/* 11 normal operation */
|
||||
CONSOLE_DEBUG_TX_STRING($ram_enable_11)
|
||||
RAM_NORMAL()
|
||||
|
||||
RET_LABEL(enable_sdram)
|
||||
|
||||
sdram_enable_out:
|
||||
|
|
@ -12,6 +12,10 @@
|
|||
#ifndef CONFIG_MAX_SPOTCHECK_ERRORS
|
||||
#define CONFIG_MAX_SPOTCHECK_ERRORS 20
|
||||
#endif
|
||||
|
||||
# debugging SMJ
|
||||
#define NO_HLT
|
||||
|
||||
spot_test: .string " Spot checking: "
|
||||
spot_error: .string "Blatant memory errors found.\r\n"
|
||||
|
||||
|
|
@ -79,15 +83,19 @@ spot_check:
|
|||
incl %esi
|
||||
cmpl $CONFIG_MAX_SPOTCHECK_ERRORS, %esi
|
||||
jbe 3b
|
||||
#ifndef NO_HLT
|
||||
5:
|
||||
CONSOLE_INFO_TX_STRING($spot_error)
|
||||
intel_chip_post_macro(0xf1)
|
||||
jmp .Lhlt
|
||||
#endif
|
||||
|
||||
6:
|
||||
#ifndef NO_HLT
|
||||
/* If any memory errors occured hlt */
|
||||
testl %esi, %esi
|
||||
jnz 5b
|
||||
#endif
|
||||
mov %ebp, %esp
|
||||
|
||||
RETSP
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue