From 46f5ad8c3a6b114206017e85b0e8cb4080c50b3c Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Thu, 2 Jun 2016 15:00:36 -0700 Subject: [PATCH] UPSTREAM: board/intel/amenia: Enable LPSS S0ix This setting will enable S0ix for LPSS BUG=None BRANCH=None TEST=None Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Original-Signed-off-by: Hannah Williams Original-Reviewed-on: https://review.coreboot.org/15056 Original-Reviewed-by: Aaron Durbin Original-Tested-by: build bot (Jenkins) Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/358833 Reviewed-by: Furquan Shaikh --- src/mainboard/intel/amenia/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f769..7045f59b5d 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # LPSS S0ix Enable + register "lpss_s0ix_enable" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF