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UPSTREAM: Revert "sb/intel/bd82x6x: Disable unused bridges"

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This reverts commit f4835a85c0. It
completely ignores port coalescing and breaks enumeration in many
cases. The code reused to disable and hide the root ports was never
meant to be called that way.

The same effect of power saving can likely be achieved by clock
gating unused ports after enumeration without further, error-prone
function hiding.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibb8c6c2143324a3d366d838234ae0b2fe317fdaa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fc20926130
Original-Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1
Original-Signed-off-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-on: https://review.coreboot.org/20216
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539211
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Nico Huber 2017-06-14 23:04:49 +02:00 • committed by chrome-bot
commit 469fdac020
1 changed files with 0 additions and 14 deletions
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14
src/southbridge/intel/bd82x6x/pcie.c
View file

@ -269,14 +269,6 @@ static void pch_pcie_enable(device_t dev)
pch_pcie_pm_early(dev);
}
static void pch_pcie_disable(device_t dev)
{
dev->enabled = 0;
/* Let PCH hide the device */
pch_enable(dev);
}
static void pch_pciexp_scan_bridge(device_t dev)
{
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
@ -286,11 +278,6 @@ static void pch_pciexp_scan_bridge(device_t dev)
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
} else {
if (!dev_is_active_bridge(dev)) {
dev->ops->disable(dev);
return;
}
}
/* Late Power Management init after bridge device enumeration */
@ -318,7 +305,6 @@ static struct device_operations device_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.disable = pch_pcie_disable,
.enable = pch_pcie_enable,
.scan_bus = pch_pciexp_scan_bridge,
.ops_pci = &pci_ops,