From 461520ace527a92a2674dc3cb1898cadb0f64f1b Mon Sep 17 00:00:00 2001 From: Li-Ta Lo Date: Tue, 28 Nov 2000 01:21:02 +0000 Subject: [PATCH] Register recommended setting tables for SiS 630 and SiS 630S --- src/northsouthbridge/sis/630/630_regs.inc | 105 ++++++ src/northsouthbridge/sis/630/630s_regs.inc | 105 ++++++ src/northsouthbridge/sis/630/ipl.S | 16 +- src/northsouthbridge/sis/630/raminit.inc | 397 ++++----------------- 4 files changed, 278 insertions(+), 345 deletions(-) create mode 100644 src/northsouthbridge/sis/630/630_regs.inc create mode 100644 src/northsouthbridge/sis/630/630s_regs.inc diff --git a/src/northsouthbridge/sis/630/630_regs.inc b/src/northsouthbridge/sis/630/630_regs.inc new file mode 100644 index 0000000000..962f88345f --- /dev/null +++ b/src/northsouthbridge/sis/630/630_regs.inc @@ -0,0 +1,105 @@ +/* + * 630_regs.inc: Register Recommended Setting for SiS 630 [ABE][01] + * + * + * Copyright 2000 Silicon Integrated Systems Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: + * 1. SiS 630 Specification + * 2. SiS 630A1 Register Recommended Setting + * Rev 0.97, Jan 7, 2000 + * + * $Id$ + */ + +northbridge_init_table: +# Reg. Value + /* generic PCI configuration space */ + .byte 0x04, 0x07 # Turn on Bus Master, + .byte 0x05, 0x00 # Memory and I/O Space + .byte 0x06, 0x00 # clear PCI status + .byte 0x07, 0x00 # + .byte 0x0D, 0x20 # Master Latency Timer = 32 PCI CLCK + + /* SiS 630 specific registers. See SiS 630 Reconnaded Registers Setting */ + + /* Host Control Interface */ + .byte 0x50, 0x9C # + .byte 0x51, 0x00 # + + /* DRAM Control */ + .byte 0x52, 0xC5 # + .byte 0x53, 0x00 # + + .byte 0x54, 0x00 # 0x00 -> 66/100 MHZ, 0x08 -> 133 MHZ + .byte 0x55, 0x29 # 0x29 -> 66/100 MHZ, 0x1D -> 133 MHZ + .byte 0x56, 0x80 # 0x00 -> 66 MHZ, 0x80 -> 100/133 MHZ + .byte 0x57, 0x00 # 0x00 -> 100 MHZ 0x01 -> 133 MHZ + + /* Pre-driver Slew Rate/Current Driving Control */ + .byte 0x58, 0x00 # + .byte 0x59, 0x35 # + .byte 0x5A, 0x51 # + .byte 0x5B, 0x00 # + + .byte 0x65, 0x00 # Use DIMM 0 for SMA + + /* MISC Control */ + .byte 0x6A, 0xC0 # + .byte 0x6B, 0x01 # 0x00 -> 66/133 MHZ, 0x01 -> 100 MHZ + .byte 0x6C, 0x20 # 0x2E -> 66 MHZ, 0x20 -> 100 MHZ, 0x2C -> 133 MHZ + + /* PCI Interface */ + .byte 0x80, 0x21 # + .byte 0x81, 0xFF # + .byte 0x82, 0x7F # + .byte 0x83, 0x1E # + + .byte 0x84, 0x60 # + .byte 0x85, 0x00 # + .byte 0x86, 0x03 # + .byte 0x87, 0x40 # + + .byte 0x88, 0x00 # + .byte 0x89, 0x08 # + + /* AGP GART Base Address */ + .byte 0x90, 0x00 + .byte 0x91, 0x00 + .byte 0x92, 0x00 + .byte 0x93, 0x00 + + /* Graphic Window Size */ + .byte 0x94, 0x40 # Graphic Window Size == 64MB + .byte 0x97, 0x01 # Page Table Cache Enable + .byte 0x98, 0x00 # + .byte 0x9C, 0x02 # CPU to VGA MEM Posted Write + + /* DRAM Priority Timer Control REgister */ + .byte 0xA0, 0x00 + .byte 0xA1, 0x00 + .byte 0xA2, 0x03 + .byte 0xA3, 0x01 + + /* AGP Command Register */ + .byte 0xC8, 0x04 # AGP 4X + .byte 0xC9, 0x00 # AGP Disabled + .byte 0xCA, 0x00 + .byte 0xCB, 0x00 + +northbridge_init_table_end: \ No newline at end of file diff --git a/src/northsouthbridge/sis/630/630s_regs.inc b/src/northsouthbridge/sis/630/630s_regs.inc new file mode 100644 index 0000000000..6b66674b62 --- /dev/null +++ b/src/northsouthbridge/sis/630/630s_regs.inc @@ -0,0 +1,105 @@ +/* + * 630s_regs.inc: Register Recommended Setting for SiS 630S + * + * + * Copyright 2000 Silicon Integrated Systems Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: + * 1. SiS 630S Specification + * 2. SiS 630S Register Recommended Setting + * Rev 0.91, September, 2000 + * + * $Id$ + */ + +pci_init_table: +# Reg. Value + /* generic PCI configuration space */ + .byte 0x04, 0x07 # Turn on Bus Master, + .byte 0x05, 0x00 # Memory and I/O Space + .byte 0x06, 0x00 # clear PCI status + .byte 0x07, 0x00 # + .byte 0x0D, 0x20 # Master Latency Timer = 32 PCI CLCK + + /* SiS 630 specific registers. See SiS 630 Reconnaded Registers Setting */ + + /* Host Control Interface */ + .byte 0x50, 0x7E # + .byte 0x51, 0x13 # + + /* DRAM Control */ + .byte 0x52, 0xC5 # + .byte 0x53, 0x0b # + + .byte 0x54, 0x00 # 0x00 -> 66/100 MHZ, 0x08 -> 133 MHZ + .byte 0x55, 0x05 # 0x05 -> 66/100 MHZ, 0x01 -> 133 MHZ + .byte 0x56, 0x80 # 0x00 -> 66 MHZ, 0x80 -> 100/133 MHZ + .byte 0x57, 0x00 # 0x00 -> 100 MHZ 0x01 -> 133 MHZ + + /* Pre-driver Slew Rate/Current Driving Control */ + .byte 0x58, 0x00 # + .byte 0x59, 0x05 # + .byte 0x5A, 0x51 # + .byte 0x5B, 0x00 # + + .byte 0x65, 0x00 # Use DIMM 0 for SMA + + /* MISC Control */ + .byte 0x6A, 0xC6 # + .byte 0x6B, 0x00 # 0x00 -> 66/133 MHZ, 0x01 -> 100 MHZ + .byte 0x6C, 0x2f # 0x2E -> 66 MHZ, 0x20 -> 100 MHZ, 0x2C -> 133 MHZ + + /* PCI Interface */ + .byte 0x80, 0x23 # + .byte 0x81, 0xFF # + .byte 0x82, 0x7F # + .byte 0x83, 0x1f # + + .byte 0x84, 0xf0 # + .byte 0x85, 0x00 # + .byte 0x86, 0x01 # + .byte 0x87, 0x40 # + + .byte 0x88, 0x00 # + .byte 0x89, 0x08 # + + /* AGP GART Base Address */ + .byte 0x90, 0x00 + .byte 0x91, 0x00 + .byte 0x92, 0x00 + .byte 0x93, 0x00 + + /* Graphic Window Size */ + .byte 0x94, 0x40 # Graphic Window Size == 64MB + .byte 0x97, 0x01 # Page Table Cache Enable + .byte 0x98, 0x00 # + .byte 0x9C, 0x80 # Enable Integrated VGA + + /* DRAM Priority Timer Control REgister */ + .byte 0xA0, 0x00 + .byte 0xA1, 0x00 + .byte 0xA2, 0x03 + .byte 0xA3, 0x01 + + /* AGP Command Register */ + .byte 0xC8, 0x04 # AGP 4X + .byte 0xC9, 0x00 # AGP Disabled + .byte 0xCA, 0x00 + .byte 0xCB, 0x00 + +pci_init_table_end: \ No newline at end of file diff --git a/src/northsouthbridge/sis/630/ipl.S b/src/northsouthbridge/sis/630/ipl.S index db84600e54..361e7afba3 100644 --- a/src/northsouthbridge/sis/630/ipl.S +++ b/src/northsouthbridge/sis/630/ipl.S @@ -2,7 +2,7 @@ * ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium * * - * Copyright 2000 Silicon Integrated System Corporation + * Copyright 2000 Silicon Integrated Systems Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -364,16 +364,16 @@ sdram_type_bank_2: .byte 0b0011, 0b0111, 0b1011, 0b1111 # 13 pci_init_table: -# Reg. Value times +# Reg. Value #include "dll.inc" - .byte 0x57, 0x80 #0x01 - .byte 0x57, 0x40 #0x01 - .byte 0x57, 0x20 #0x06 - .byte 0x57, 0x20 #0x06 - .byte 0x57, 0x20 #0x06 - .byte 0x52, 0x01 #0x01 + .byte 0x57, 0x80 # Precharge + .byte 0x57, 0x40 # Mode Register Set + .byte 0x57, 0x20 # Refresh + .byte 0x57, 0x20 # Refresh + .byte 0x57, 0x20 # Refresh + .byte 0x52, 0x01 # Refresh Cycle Enable .byte 0x00 /* Null, End of table */ .org 0x01f0 diff --git a/src/northsouthbridge/sis/630/raminit.inc b/src/northsouthbridge/sis/630/raminit.inc index 3cad0a7584..9fe73c8109 100644 --- a/src/northsouthbridge/sis/630/raminit.inc +++ b/src/northsouthbridge/sis/630/raminit.inc @@ -1,352 +1,75 @@ /* -This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described -here. The SOFTWARE has been approved for release with associated -LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has -been authored by an employee or employees of the University of -California, operator of the Los Alamos National Laboratory under -Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The -U.S. Government has rights to use, reproduce, and distribute this -SOFTWARE. The public may copy, distribute, prepare derivative works -and publicly display this SOFTWARE without charge, provided that this -Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express -or implied, or assumes any liability or responsibility for the use of -this SOFTWARE. If SOFTWARE is modified to produce derivative works, -such modified SOFTWARE should be clearly marked, so as not to confuse -it with the version available from LANL. + * raminit.inc: Setting registers to their recommended values for SiS 630. + * Since we have inited the DRAM in IPL it is not neceressary + * to do "raminit" here any more. + * + * + * Copyright 2000 Silicon Integrated Systems Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: + * 1. SiS 630 Specification + * 2. SiS 630A1 Register Recommended Setting + * Rev 0.97, Jan 7, 2000 + * + * $Id$ */ -/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * rminnich@lanl.gov - */ -/* this set of steps is REQUIRED before you do anything to DRAM */ - /* Reg name Power-on dflt*/ - CS_WRITE(SIS_PCMC_REG04,$0x07) - CS_WRITE(SIS_PCMC_REG05,$0x00) - CS_WRITE(SIS_PCMC_REG06,$0x00) - CS_WRITE(SIS_PCMC_REG07,$0x02) - CS_WRITE(SIS_PCMC_REG0C,$0x00) - CS_WRITE(SIS_PCMC_REG0D,$0x20) - CS_WRITE(SIS_PCMC_REG0E,$0x00) - CS_WRITE(SIS_PCMC_REG0F,$0x00) - CS_WRITE(SIS_PCMC_REG50,$0x09C) - CS_WRITE(SIS_PCMC_REG51,$0x000) - CS_WRITE(SIS_PCMC_REG52,$0x0C5) - CS_WRITE(SIS_PCMC_REG53,$0x000) - CS_WRITE(SIS_PCMC_REG54,$0x000) /** 00h (66/100), 08h (133)*/ - CS_WRITE(SIS_PCMC_REG55,$0x029) /** 29h (100), 1Dh (133)*/ - CS_WRITE(SIS_PCMC_REG56,$0x080) /** 00h (66), 80h (100/133) */ - /*CS_WRITE(SIS_PCMC_REG57,$0x000) */ /* 000h (100||VCM), 001h (133)*/ - /* temporary change ... set it to 1, since the bst1b does that too */ +#define PCI_COMMAND_PORT 0xcf8 +#define PCI_DATA_PORT 0xcfc -#ifndef USE_DOC_MIL - CS_WRITE(SIS_PCMC_REG57,$0x001) /** 000h (100||VCM), 001h (133)*/ -#endif - CS_WRITE(SIS_PCMC_REG58,$0x000) - CS_WRITE(SIS_PCMC_REG59,$0x035) - CS_WRITE(SIS_PCMC_REG5A,$0x051) - CS_WRITE(SIS_PCMC_REG5B,$0x000) +#define NORTH_BRIDGE_BASE_ADDR 0x80000000 -#ifndef USE_DOC_MIL - CS_WRITE(SIS_PCMC_REG63,$0x000) -#endif - - /* This is needed for SiSfb. Shared memory is in dimm 0. */ - CS_WRITE(SIS_PCMC_REG65,$0x000) - CS_WRITE(SIS_PCMC_REG6A,$0x0C0) - CS_WRITE(SIS_PCMC_REG6B,$0x001) /** 000h (66/133), 001h (100)*/ - CS_WRITE(SIS_PCMC_REG6C,$0x020) /** 02Eh (66), 020h (100), 02Ch (133)*/ - CS_WRITE(SIS_PCMC_REG70,$0x000) /* Shadow register*/ - CS_WRITE(SIS_PCMC_REG71,$0x080) /* Shadow register*/ - CS_WRITE(SIS_PCMC_REG72,$0x000) /* Shadow register*/ - CS_WRITE(SIS_PCMC_REG73,$0x000) /* Shadow register*/ - -#ifdef NOTUSED - CS_WRITE(SIS_PCMC_REG74,$0x000) /* Shadow register*/ - CS_WRITE(SIS_PCMC_REG75,$0x010) /* Shadow register*/ -#endif - - CS_WRITE(SIS_PCMC_REG80,$0x021) - CS_WRITE(SIS_PCMC_REG81,$0x0FF) - CS_WRITE(SIS_PCMC_REG82,$0x07F) - CS_WRITE(SIS_PCMC_REG83,$0x01E) - CS_WRITE(SIS_PCMC_REG84,$0x060) - CS_WRITE(SIS_PCMC_REG85,$0x000) - CS_WRITE(SIS_PCMC_REG86,$0x003) - CS_WRITE(SIS_PCMC_REG87,$0x040) - CS_WRITE(SIS_PCMC_REG88,$0x000) - CS_WRITE(SIS_PCMC_REG89,$0x008) - -#ifndef USE_DOC_MIL - CS_WRITE(SIS_PCMC_REG8C,$0x066) - CS_WRITE(SIS_PCMC_REG8D,$0x066) - CS_WRITE(SIS_PCMC_REG8E,$0x003) /** default=03h for 100/133, recommend=00h*/ - CS_WRITE(SIS_PCMC_REG8F,$0x055) -#endif - - CS_WRITE(SIS_PCMC_REG90,$0x000) - CS_WRITE(SIS_PCMC_REG91,$0x000) - CS_WRITE(SIS_PCMC_REG92,$0x000) - CS_WRITE(SIS_PCMC_REG93,$0x000) - CS_WRITE(SIS_PCMC_REG94,$0x040) - CS_WRITE(SIS_PCMC_REG97,$0x001) - CS_WRITE(SIS_PCMC_REG98,$0x000) - CS_WRITE(SIS_PCMC_REG9C,$0x002) - CS_WRITE(SIS_PCMC_REGA0,$0x000) - CS_WRITE(SIS_PCMC_REGA1,$0x000) - CS_WRITE(SIS_PCMC_REGA2,$0x003) - CS_WRITE(SIS_PCMC_REGA3,$0x001) - CS_WRITE(SIS_PCMC_REGA5,$0x000) - CS_WRITE(SIS_PCMC_REGA6,$0x000) - CS_WRITE(SIS_PCMC_REGA7,$0x000) - CS_WRITE(SIS_PCMC_REGA8,$0x000) - CS_WRITE(SIS_PCMC_REGA9,$0x000) - CS_WRITE(SIS_PCMC_REGAA,$0x000) - CS_WRITE(SIS_PCMC_REGAB,$0x000) - CS_WRITE(SIS_PCMC_REGAC,$0x000) - CS_WRITE(SIS_PCMC_REGC8,$0x004) - CS_WRITE(SIS_PCMC_REGC9,$0x000) - CS_WRITE(SIS_PCMC_REGCA,$0x000) - CS_WRITE(SIS_PCMC_REGCB,$0x000) - -#ifdef SIS630S - CS_WRITE(SIS_PCMC_REG50, $0x7e) - CS_WRITE(SIS_PCMC_REG51, $0x13) - CS_WRITE(SIS_PCMC_REG53, $0x0b) - CS_WRITE(SIS_PCMC_REG55, $0x05) - CS_WRITE(SIS_PCMC_REG59, $0x05) - CS_WRITE(SIS_PCMC_REG6A, $0xc6) - CS_WRITE(SIS_PCMC_REG6B, $0x00) - CS_WRITE(SIS_PCMC_REG6C, $0x2f) - CS_WRITE(SIS_PCMC_REG71, $0x00) - CS_WRITE(SIS_PCMC_REG80, $0x23) - CS_WRITE(SIS_PCMC_REG83, $0x1f) - CS_WRITE(SIS_PCMC_REG84, $0xf0) - CS_WRITE(SIS_PCMC_REG86, $0x01) - CS_WRITE(SIS_PCMC_REG9C, $0x80) -#endif /* SIS630S */ +register_setting_start: + movl $northbridge_init_table, %esi + movl $(northbridge_init_table_end - northbridge_init_table), %ecx + shrl $0x01, %ecx -#ifndef USE_DOC_MIL -/* this sequence gets the SiS 630 ram up and running, we hope. */ -/* for now, let's stick to bank 0, and jam the size to 64M, 2 side (128M) */ -/* the sizing is not hard, but we need an opinion from SiS on whether - * they would prefer to write it. They can do this better than we can. - */ - /* post 0x01 to 0x80 port for debugging */ - intel_chip_post_macro(0x01) +init_northbridge: + movw (%esi), %ax # load the register address/value to %ax + xchgb %al, %ah # exchange address/values for write_common + call write_northbridge_register - movb $0xBF, %al /* Bit 7 controls NMI*/ - outb %al, $0x70 /* Disable NMI interrupts */ + addl $0x02, %esi + decl %ecx + loopnz init_northbridge - movw $0x0, %si - movw $0x0, %di + jmp register_setting_end -OtherBank: +write_northbridge_register: + /* Input: AH - register number. AL - register value. */ + movl $NORTH_BRIDGE_BASE_ADDR, %edx - /* registers we use: eax, cl, and dx */ - /* parameters: at some point, cl will be the bank # */ - /* returns: none */ +write_common: + movl %eax, %ebx # Save %ax to %cx. - /* note: the macros trash cl, eax and dx. Nothing else gets - * hurt. So to subroutine-ify them you can call with things in - * ebx and ch. So you could have the bank in ch and return in ebx - * For now, this is in-line code until we think we know what we're - * doing. - */ - /* for now, we don't try to autosize - * We know the size -- 64M X 2 - */ + movzbl %bh, %eax # add register address to + addl %edx, %eax # PCI base address - /* turn on dimm 0 */ - movw %si, %cx - movw $0x1, %ax - shlw %cl, %ax - movw %ax, %bx - CS_WRITE(SIS_PCMC_REG63, %bl) - movw %cx, %si + movw $PCI_COMMAND_PORT, %dx + outl %eax, %dx - /* make it the max size configuration */ - movw %si, %bx - addw SIS_PCMC_REG60, %si - CS_WRITE(%si, DRAM_MAXSIZE) - movw %bx, %si + movw $PCI_DATA_PORT, %dx + andb $0x03, %al + addb %al, %dl + movb %bl, %al + outb %al, %dx + ret # End of write_[lpc|pci]_reg - /* disable refresh */ - REGBIC(SIS_PCMC_REG52, REFRESH_ENABLE) - /* mode register set */ - REGBIS(SIS_PCMC_REG57, MRS) - /* precharge */ - REGBIS(SIS_PCMC_REG57, PRECHARGE) - /* refresh command */ - /* the question is, will these cause trouble back-to-back */ - /* not really, because this is a macro, so we have lots of insns - * between sets - * macros sometimes win - * 16 refresh commands - */ - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) - REGBIS(SIS_PCMC_REG57, REFRESH) +#include "630_regs.inc" - /* now turn refresh back on */ - REGBIS(SIS_PCMC_REG52, REFRESH_ENABLE) - - /* now write some data to the sdram. This is required by the - * pc100 spec. The specific patterns vary by mainboard ... - * the jmp's are cheap delays, back-to-back writes at this point - * may be a problem. - */ - movl MPATTERN0, %eax - movl %eax, 0 - movl SDPATTERN1, %eax - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: movl %eax, 0x8 - jmp 1f -1: - movl MPATTERN0, %eax - cmpl 0, %eax - jmp 1f -1: jne noram - - movl MPATTERN1, %eax - movl %eax, 0x40000000-0x10 - movl SDPATTERN1, %eax - movl %eax, 0x40000000-0x8 - movl MPATTERN1, %eax - cmpl %eax, 0x40000000-0x10 - jne 1f - - /* save drame type of this slot - * in bit 15-31 of %ecx */ - movb $0x20, %cl - shll $0x10, %ecx - jmp doubleside -1: - mov $0x00, %cl - shll $0x10,%ecx - -doubleside: - movw %di, %bx - movw $0x1, %di - movw %si, %cx - shlw %cl, %di - orw %bx, %di - - /* FIXME: why do we have this two ?? */ - movl SDPATTERN1, %eax - cmpl 8, %eax - - CALLSP(sizeram630) - shrl $0x10, %ecx - movb %al, %ch - orb %cl, %ch - - movw %si, %bx - addw SIS_PCMC_REG60, %si - CS_WRITE(%si, %ch) - movw %bx, %si - incw %si - - /* this appears to be trouble, so we'll skip it for now. RGM */ -#if 1 - cmpw $0x03, %si - je done - jmp OtherBank -#else - jmp done -#endif - -#define CMPBRANCH(address, target) cmp %eax, address; jne target -#define CMPEQRETURN(address, value) cmp %eax, address; jne 1f; mov value, %eax; RETSP; 1: -#define CMPNERETURN(address, value) cmp %eax, address; je 1f; mov value, %eax; RETSP; 1: -#define RETURN(value) mov value, %eax; RETSP - -sizeram630: - movl MPATTERN0, %eax - movl %eax, 0 - CMPBRANCH(0x1000, SMA2) - CMPBRANCH(0x800000, SMA_1_1x_0910) - CMPEQRETURN(0x4000000, SMA_1_11_08) - RETURN(SMA_1_13_08) -SMA_1_1x_0910: - CMPBRANCH(0x1000000, SMA_1_xx_10) - CMPEQRETURN(0x4000000, SMA_1_11_09) - RETURN(SMA_1_13_09) -SMA_1_xx_10: - CMPNERETURN(0x8000000, SMA_1_13_11) - CMPEQRETURN(0x4000000, SMA_1_11_10) - RETURN(SMA_1_13_10) -SMA2: CMPBRANCH(0x800000, SMA_2_xx_091011) - CMPNERETURN(0x10000000, SMA_2_13_08) - CMPEQRETURN(0x4000000, SMA_2_11_08) - RETURN(SMA_2_12_08) -SMA_2_xx_091011: - CMPBRANCH(0x1000000, SMA_2_xx_1011) - CMPEQRETURN(0x10000000, SMA_2_12_09) - RETURN(SMA_2_13_09) -SMA_2_xx_1011: - CMPBRANCH(0x8000000, SMA_2_xx_11) - CMPEQRETURN(0x10000000, SMA_2_12_10) - RETURN(SMA_2_13_10) -SMA_2_xx_11: - CMPEQRETURN(0x10000000, SMA_2_12_11) - movl MPATTERN1, %eax - movl %eax, 0x20000000 - CMPEQRETURN(0x20000000, SMA_2_13_11) - -noram: - incw %si - cmpw $0x03,%si - je done - jmp OtherBank - -done: - movl $0x80000060, %eax - movw $0x0cf8, %dx - outl %eax, %dx - movw $0x0cff, %dx - movw %di, %ax - outb %al, %dx - -#ifdef SIS630 -#ifdef SIS_FIXUP_FOR_FB - // make shared memory between the agp and the processor - movl $0x80000060, %eax - movw $0x0cf8, %dx - outl %eax, %dx - movw $0x0cff, %dx - inb %dx, %al - orb $0x90, %al - outb %al, %dx -#endif /* SIS_FIXUP_FOR_FB */ -#endif /* SIS630 */ - -#endif /* USE_DOC_MIL */ +register_setting_end: \ No newline at end of file