Get it to build, this is as far as I want to take this board with its

obsolete chip.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@891 f3766cd6-281f-0410-b1cd-43a5c92072e9

mainboard/gigabyte/m57sli/Makefile

@@ -25,16 +25,19 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
-			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
-			$(src)/northbridge/amd/k8/coherent_ht.c \
-			$(src)/northbridge/amd/k8/incoherent_ht.c \
+			$(src)/northbridge/amd/k8/get_nodes.c \
+			$(src)/northbridge/amd/k8/incoherent_ht_chain.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
+			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
+			$(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
 			$(src)/northbridge/amd/k8/reset_test.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
+			$(src)/northbridge/amd/k8/incoherent_ht.c \
+			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/arch/x86/amd/model_fxx/dualcore.c \
 			$(src)/arch/x86/amd/model_fxx/fidvid.c \
 			$(src)/arch/x86/amd/model_fxx/init_cpus.c \

mainboard/gigabyte/m57sli/initram.c

@@ -30,15 +30,14 @@
 #include <msr.h>
 #include <io.h>
 #include <cpu.h>
+#include <globalvars.h>
 #include <amd/k8/k8.h>
 #include <southbridge/nvidia/mcp55/mcp55_smbus.h>
 #include <mc146818rtc.h>
 #include <spd.h>
 
-# warning fix hard_reset
-void hard_reset(void)
-{
-}
+void hard_reset(void);
+
 void memreset_setup(void)
 {
 }
@@ -58,9 +57,99 @@ void activate_spd_rom(const struct mem_controller *ctrl)
   */
 int main(void)
 {
-	printk(BIOS_DEBUG, "Hi there from stage1\n");
-	post_code(POST_START_OF_MAIN);
+	void enable_smbus(void);
+	void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn);
+	void soft_reset_x(unsigned sbbusn, unsigned sbdn);
+	int cpu_init_detected(unsigned int nodeid);
+	void start_all_cores(void);
+	void set_sysinfo_in_ram(unsigned val);
+	int mcp55_early_setup_x(void);
+	void soft_reset(void);
 
-	printk(BIOS_DEBUG, "stage1 returns\n");
+	struct msr msr;
+	static const u16 spd_addr[] = {
+		(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
+		(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
+		(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+#endif
+	};
+	struct sys_info *sysinfo = &(global_vars()->sys_info);
+
+	int needs_reset = 0;
+	unsigned bsp_apicid = 0;
+	int init_detected;
+	struct node_core_id me;
+
+	me = get_node_core_id();
+	printk(BIOS_DEBUG, "Hi there from stage1, cpu%d, core%d\n", me.nodeid, me.coreid);
+
+	init_detected = cpu_init_detected(me.nodeid);
+	printk(BIOS_DEBUG, "init_detected: %d\n", init_detected);
+	/* well, here we are. For starters, we need to know if this is cpu0 core0. 
+	 * cpu0 core 0 will do all the DRAM setup. 
+	 */
+	bsp_apicid = init_cpus(init_detected, sysinfo);
+
+	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
+
+	set_sysinfo_in_ram(0);	// in BSP so could hold all ap until sysinfo is in ram
+	setup_coherent_ht_domain();	// routing table and start other core0
+
+	wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+	// It is said that we should start core1 after all core0 launched
+	/* because optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+	 * So here need to make sure last core0 is started, esp for two way system,
+	 * (there may be apic id conflicts in that case)
+	 */
+	start_all_cores();
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	/* it will set up chains and store link pair for optimization later */
+	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
+
+	msr = rdmsr(FIDVID_STATUS);
+	printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", msr.hi, msr.lo);
+
+
+	enable_fid_change();
+
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+	init_fidvid_bsp(bsp_apicid);
+
+	msr = rdmsr(FIDVID_STATUS);
+	printk(BIOS_DEBUG, "end msr fid, vid %08x:%08x\n", msr.hi, msr.lo);
+
+
+	needs_reset |= optimize_link_coherent_ht();
+	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	needs_reset |= mcp55_early_setup_x();
+
+	// fidvid change will issue one LDTSTOP and the HT change will be effective too
+	if (needs_reset) {
+		printk(BIOS_INFO, "ht reset -\n");
+		soft_reset();
+	}
+	allow_all_aps_stop(bsp_apicid);
+
+	//It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	enable_smbus();
+
+	memreset_setup();
+
+	//do we need apci timer, tsc...., only debug need it for better output
+	/* all ap stopped? */
+//        init_timer(); // Need to use TMICT to synconize FID/VID
+
+	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+	printk(BIOS_DEBUG, "initram returns\n");
 	return 0;
 }
+

mainboard/gigabyte/m57sli/mainboard.h

@@ -46,3 +46,6 @@
 
 /* you don't want to set this in Kconfig or dts either. It's dangerous! */
 #define CONFIG_AP_CODE_IN_CAR 0
+/* MCP55 is another fun challenge */
+#define MCP55_NUM 1
+#define MCP55_DEVN_BASE	HT_CHAIN_UNITID_BASE

mainboard/gigabyte/m57sli/stage1.c

@@ -295,11 +295,12 @@ static const struct rmap register_values[] = {
 
 	};
 
-
 void hardware_stage1(void)
 {
 	void it8716f_enable_serial(u8 dev, u8 serial, u16 iobase);
 	void enumerate_ht_chain(void);
+	void sio_setup(u32 devn);
+	void mcp55_enable_rom(void);
 	int max;
 	u8 tmp;
 
@@ -325,6 +326,8 @@ void hardware_stage1(void)
 
 	setup_resource_map(register_values, max);
 	enumerate_ht_chain();
+	sio_setup(MCP55_DEVN_BASE);
+	mcp55_enable_rom();
 	printk(BIOS_ERR, "Done.\n");
 	post_code(POST_START_OF_MAIN);