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UPSTREAM: intel/i945: Use "IS_ENABLED" for fsbclk & memclk

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16958
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b
Reviewed-on: https://chromium-review.googlesource.com/397903
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Elyes HAOUAS 2016-10-09 20:24:20 +02:00 • committed by chrome-bot
commit 44ff98336a
1 changed files with 18 additions and 23 deletions
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41
src/northbridge/intel/i945/raminit.c
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@ -106,10 +106,8 @@ void sdram_dump_mchbar_registers(void)
static int memclk(void)
{
int offset = 0;
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
offset++;
#endif
int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
case 1: return 400;
case 2: return 533;
@ -119,29 +117,26 @@ static int memclk(void)
return -1;
}
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 400;
case 1: return 533;
case 3: return 667;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 400;
case 1: return 533;
case 3: return 667;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
} else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 1066;
case 1: return 533;
case 2: return 800;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
}
return 0xffff;
}
#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
static u16 fsbclk(void)
{
switch (MCHBAR32(CLKCFG) & 7) {
case 0: return 1066;
case 1: return 533;
case 2: return 800;
default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
}
return 0xffff;
}
#endif
static int sdram_capabilities_max_supported_memory_frequency(void)
{