diff --git a/src/soc/intel/snowridge/include/soc/pci_devs.h b/src/soc/intel/snowridge/include/soc/pci_devs.h
index ca50bf8eb1..09336c0724 100644
--- a/src/soc/intel/snowridge/include/soc/pci_devs.h
+++ b/src/soc/intel/snowridge/include/soc/pci_devs.h
@@ -68,6 +68,12 @@
 
 /* Stack U0. */
 #define UBOX_DEV_RACU   _UBOX0_DEV(0x00, 1)
+
+#define SMM_FEATURE_CONTROL		0x8c
+#define  SMM_CODE_CHK_EN		BIT(2)
+#define  SMM_FC_CPU_SAVE_EN		BIT(1)
+#define  SMM_FEATURE_CONTROL_LOCK	BIT(0)
+
 #define UBOX_DEV_NCDECS _UBOX0_DEV(0x00, 2)
 
 /* Stack U1. */
diff --git a/src/soc/intel/snowridge/lockdown.c b/src/soc/intel/snowridge/lockdown.c
index b74b74ca4b..485d3413d3 100644
--- a/src/soc/intel/snowridge/lockdown.c
+++ b/src/soc/intel/snowridge/lockdown.c
@@ -8,10 +8,6 @@
 #include <soc/pm.h>
 #include <soc/pmc.h>
 
-#define SMM_FEATURE_CONTROL      0x8c
-#define SMM_CODE_CHK_EN          (1 << 2)
-#define SMM_FEATURE_CONTROL_LOCK (1 << 0)
-
 static void pmc_lockdown_cfg(int chipset_lockdown)
 {
 	pmc_or_mmio32(PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);