From 44d7b9655d53823668bc6101be70627985f6123e Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 3 Oct 2016 16:05:20 -0700 Subject: [PATCH] UPSTREAM: soc/intel/apollolake: Disable HECI2 device reset on S3 resume Converged Security Engine (CSE) has a secure variable storage feature. However, this storage is expected to be reset during S3 resume flow. Since coreboot does not use secure storage feature, disable HECI2 reset request. This saves appr. 130ms of resume time. BUG=chrome-os-partner:56941 BRANCH=none TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note FspMemoryInit time is not significantly different from normal boot time case. Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/16870 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233 Reviewed-on: https://chromium-review.googlesource.com/396226 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2384ceb1cf..1f6a38fecc 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -184,6 +184,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + + /* + * Converged Security Engine (CSE) has secure storage functionality. + * HECI2 device can be used to access that functionality. However, part + * of S3 resume flow involves resetting HECI2 which takes 136ms. Since + * coreboot does not use secure storage functionality, instruct FSP to + * skip HECI2 reset. + */ + mupd->FspmConfig.EnableS3Heci2 = 0; } __attribute__ ((weak))