From 44901340bf88f2e16463b1e14b03a9f4e3bf0984 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 27 Feb 2026 22:43:48 +0100 Subject: [PATCH] sb/intel/wildcatpoint/pcie.c: Ensure OBFF is disabled For consistency with Lynx Point, ensure OBFF is disabled in DCTL2. Change-Id: Id726ade900adfce513ad58c77027de8862bd271b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/91471 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/southbridge/intel/wildcatpoint/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/wildcatpoint/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c index 9262d3c628..ada269fc73 100644 --- a/src/southbridge/intel/wildcatpoint/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -517,7 +517,7 @@ static void pch_pcie_early(struct device *dev) /* Enable LTR in Root Port. Disable OBFF. */ pci_update_config32(dev, 0x64, ~(3 << 18), (1 << 11)); - pci_or_config32(dev, 0x68, 1 << 10); + pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10); pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));