From 44322ed5a33ded76a378fa68ebc852f8eff649b3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 16 Sep 2016 11:15:49 -0500 Subject: [PATCH] UPSTREAM: soc/intel/apollolake: cache boot media post romstage When the boot media is memory mapped mark it as cacheable after romstage. Otherwise the boot media is uncacheable and all loads from it take longer. Loading FSP-S alone in ramstage went down to 17.5ms from 54ms. BUG=chrome-os-partner:56656 BRANCH=None TEST=None Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16613 Reviewed-by: Andrey Petrov Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33 Reviewed-on: https://chromium-review.googlesource.com/386274 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/romstage.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ebd6287e4a..b9733defa3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -130,6 +130,11 @@ asmlinkage void car_stage_entry(void) assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + /* Cache the memory-mapped boot media. */ + if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) + postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); + run_postcar_phase(&pcf); }