From 43d5f7057632346b3a5956866c94b6d5e49a1d89 Mon Sep 17 00:00:00 2001 From: Uwe Poeche Date: Thu, 10 Jul 2025 13:08:19 +0200 Subject: [PATCH] mb/siemens/mc_ehl6: Enable PTM for all enabled PCIe RPs Enable PCIe PTM (Precision Time Measurement) for all enabled PCIe root ports. The time synchronization is mainly necessary for stable timing to PLC. TEST Boot in a standard linux OS and check if PTM ist enabled for active RPs via lspci -vv -s 00:1c.0..6 | grep PTM Change-Id: I965ab349c07158d0c69b9112571aa98575eada77 Signed-off-by: Uwe Poeche Reviewed-on: https://review.coreboot.org/c/coreboot/+/90084 Reviewed-by: Mario Scheithauer Tested-by: build bot (Jenkins) Reviewed-by: Kilian Krause --- .../siemens/mc_ehl/variants/mc_ehl6/devicetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb index 2e7f0c0a72..9b21d381e0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb @@ -68,6 +68,13 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true" + # Enable PCIe PTM (Precision Time Measurement) for all PCIe root ports + register "PciePtm[0]" = "true" + register "PciePtm[1]" = "true" + register "PciePtm[2]" = "true" + register "PciePtm[4]" = "true" + register "PciePtm[6]" = "true" + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1"