diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 931cef4218..014d939160 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -753,6 +753,15 @@ config BOARD_GOOGLE_ZYDRON select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE +config BOARD_GOOGLE_EPIC + select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_TWINLAKE + if BOARD_GOOGLE_BRYA_COMMON config BASEBOARD_DIR @@ -851,6 +860,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_TELITH default 0x0 if BOARD_GOOGLE_PUJJOGATWIN default 0x0 if BOARD_GOOGLE_MELIKS + default 0x0 if BOARD_GOOGLE_EPIC config DRIVER_TPM_I2C_ADDR hex @@ -935,6 +945,7 @@ config TPM_TIS_ACPI_INTERRUPT default 13 if BOARD_GOOGLE_TELITH default 13 if BOARD_GOOGLE_PUJJOGATWIN default 13 if BOARD_GOOGLE_MELIKS + default 13 if BOARD_GOOGLE_EPIC config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN @@ -1027,6 +1038,7 @@ config MAINBOARD_PART_NUMBER default "Telith" if BOARD_GOOGLE_TELITH default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN default "Meliks" if BOARD_GOOGLE_MELIKS + default "Epic" if BOARD_GOOGLE_EPIC config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -1104,6 +1116,7 @@ config VARIANT_DIR default "telith" if BOARD_GOOGLE_TELITH default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN default "meliks" if BOARD_GOOGLE_MELIKS + default "epic" if BOARD_GOOGLE_EPIC config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index ac4c262d78..5431cba4c3 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -226,3 +226,6 @@ config BOARD_GOOGLE_TELITH config BOARD_GOOGLE_MELIKS bool "-> Meliks" + +config BOARD_GOOGLE_EPIC + bool "-> Epic" diff --git a/src/mainboard/google/brya/variants/epic/Makefile.mk b/src/mainboard/google/brya/variants/epic/Makefile.mk new file mode 100644 index 0000000000..44792c487d --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/Makefile.mk @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-y += variant.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/epic/fw_config.c b/src/mainboard/google/brya/variants/epic/fw_config.c new file mode 100644 index 0000000000..4eed44cb25 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/fw_config.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +static const struct pad_config lte_disable_pads_gothrax[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* E13 : WWAN_EN */ + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +static const struct pad_config wfc_disable_pads[] = { + /* R6 : DMIC_WCAM_CLK_R */ + PAD_NC(GPP_R6, NONE), + /* R7 : DMIC_WCAM_DATA */ + PAD_NC(GPP_R7, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!(fw_config_probe(FW_CONFIG(DB_USB, DB_C_A_LTE)) || + fw_config_probe(FW_CONFIG(DB_USB, DB_A_HDMI_LTE)))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on gothrax.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads_gothrax, + ARRAY_SIZE(lte_disable_pads_gothrax)); + } + + if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) { + printk(BIOS_INFO, "Disable WFC GPIO pins.\n"); + gpio_padbased_override(padbased_table, wfc_disable_pads, + ARRAY_SIZE(wfc_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/epic/gpio.c b/src/mainboard/google/brya/variants/epic/gpio.c new file mode 100644 index 0000000000..ae236fbe1c --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/gpio.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* H3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + + /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 1, DEEP), + + /* D3 : WCAM_RST_L */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D15 : EN_PP2800_WCAM_X */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : EN_PP1800_PP1200_WCAM_X */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H22 : WCAM_MCLK_R */ + PAD_NC(GPP_H22, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/epic/include/variant/ec.h b/src/mainboard/google/brya/variants/epic/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/brya/variants/epic/include/variant/gpio.h b/src/mainboard/google/brya/variants/epic/include/variant/gpio.h new file mode 100644 index 0000000000..9b6b711f3c --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/include/variant/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define WWAN_FCPO GPP_E13 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + +#endif diff --git a/src/mainboard/google/brya/variants/epic/memory/Makefile.mk b/src/mainboard/google/brya/variants/epic/memory/Makefile.mk new file mode 100644 index 0000000000..99db10e40b --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/epic/memory src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt new file mode 100644 index 0000000000..17a6ba6db5 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/memory/dram_id.generated.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/epic/memory src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H58G56AK6BX069 1 (0001) +K3LKBKB0BM-MGCP 2 (0010) +H9JCNNNBK3MLYR-N6E 0 (0000) +H9JCNNNCP3MLYR-N6E 3 (0011) diff --git a/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt new file mode 100644 index 0000000000..5d050345ae --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/memory/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name + +MT62F512M32D2DR-031 WT:B, +H58G56AK6BX069,*1 +K3LKBKB0BM-MGCP, +H9JCNNNBK3MLYR-N6E, +H9JCNNNCP3MLYR-N6E, diff --git a/src/mainboard/google/brya/variants/epic/overridetree.cb b/src/mainboard/google/brya/variants/epic/overridetree.cb new file mode 100644 index 0000000000..dcd8593098 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/overridetree.cb @@ -0,0 +1,556 @@ +fw_config + field DB_USB 0 2 + option DB_NONE 0 + option DB_C_A 1 + option DB_C_A_LTE 2 + option DB_A 3 + option DB_A_HDMI_LTE 6 + end + field WLAN 3 4 + option WLAN_MT7921_AZUREWAVE 0 + option WLAN_AX211_Intel 1 + end + field AUDIO 5 6 + option AUDIO_ALC1019_ALC5682IVS 0 + end + field STYLUS 7 + option STYLUS_ABSENT 0 + option STYLUS_PRESENT 1 + end + field WFC 8 + option WFC_PRESENT 0 + option WFC_ABSENT 1 + end + field TOUCH_PANEL 9 10 + option TOUCH_PANEL_I2C_HID 0 + option TOUCH_PANEL_DISABLE 1 + option TOUCH_PANEL_I2C_GENERIC 2 + end + field ADP_VOL_LIM 11 + option ADP_VOL_LIM_MAX15 0 + option ADP_VOL_LIM_MAX20 1 + end + field THERMAL_SOLUTION 22 + option THERMAL_SOLUTION_PASSIVE 0 + option THERMAL_SOLUTION_ACTIVE 1 + end +end + +chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 152, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + # TODO: below values are initial reference values only + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN7B13"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on + probe TOUCH_PANEL TOUCH_PANEL_I2C_HID + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ILI2901"" + register "generic.desc" = ""ILI Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "200" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x41 on + probe TOUCH_PANEL TOUCH_PANEL_I2C_HID + end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "detect" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "150" + register "reset_off_delay_ms" = "1" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "6" + register "has_power_resource" = "1" + register "use_gpio_for_status" = "true" + device i2c 10 on + probe TOUCH_PANEL TOUCH_PANEL_I2C_GENERIC + end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR2 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x01" + register "reg_afe_ctrl4" = "0x46" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_prox_ctrl0" = "0x09" + register "reg_prox_ctrl1" = "0x12" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x12" + register "reg_prox_ctrl6" = "0x1e" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x5c" + register "reg_adv_ctrl11" = "0x52" + register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0xf0" + register "reg_adv_ctrl20" = "0xf0" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "512" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "1" + register "ph23_proxraw_strength" = "1" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""gnd"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "3" + device i2c 28 on + probe DB_USB DB_C_A_LTE + probe DB_USB DB_A_HDMI_LTE + end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end + + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""PIXART Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pcie_rp7 on + # Enable SD Card PCIe 7 using clk 3 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on + probe DB_USB DB_C_A + probe DB_USB DB_C_A_LTE + end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on + probe DB_USB DB_C_A + probe DB_USB DB_C_A_LTE + end + end + end + end + end + device ref xhci on + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on + probe DB_USB DB_C_A + probe DB_USB DB_C_A_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on + probe DB_USB DB_C_A_LTE + probe DB_USB DB_A_HDMI_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on + probe WFC WFC_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on + probe DB_USB DB_C_A_LTE + probe DB_USB DB_A_HDMI_LTE + end + end + end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/epic/variant.c b/src/mainboard/google/brya/variants/epic/variant.c new file mode 100644 index 0000000000..033abc7788 --- /dev/null +++ b/src/mainboard/google/brya/variants/epic/variant.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (!(fw_config_probe(FW_CONFIG(DB_USB, DB_C_A_LTE)) || + fw_config_probe(FW_CONFIG(DB_USB, DB_A_HDMI_LTE)))) { + printk(BIOS_INFO, "Disable usb2_port5 and usb3_port3 of WWAN.\n"); + + config->usb2_ports[4] = (struct usb2_port_config) USB2_PORT_EMPTY; + config->usb3_ports[2] = (struct usb3_port_config) USB3_PORT_EMPTY; + } + + if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) { + printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n"); + + config->usb2_ports[6] = (struct usb2_port_config) USB2_PORT_EMPTY; + } + + if (fw_config_probe(FW_CONFIG(DB_USB, DB_A)) || fw_config_probe(FW_CONFIG(DB_USB, DB_A_HDMI_LTE))) { + printk(BIOS_INFO, "Disable typec aux_bias_pads in the SOC.\n"); + config->typec_aux_bias_pads[1].pad_auxp_dc = 0x00; + config->typec_aux_bias_pads[1].pad_auxn_dc = 0x00; + } +}