run uart_init() from console_init, just like the other console initialization functions.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/bimini_fam10/romstage.c

@@ -109,7 +109,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	enable_rs780_dev8();
 	sb800_lpc_init();
 
-	uart_init();
 	console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);

src/mainboard/amd/db800/romstage.c

@@ -69,7 +69,6 @@ void main(unsigned long bist)
 	 * early MSR setup for CS5536.
 	 */
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	uart_init();
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/amd/dbm690t/romstage.c

@@ -92,7 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* it8712f_enable_serial does not use its 1st parameter. */
 	it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
-	uart_init();
 
 	console_init();
 

src/mainboard/amd/inagua/romstage.c

@@ -56,7 +56,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
     post_code(0x31);
     kbc1100_early_init(CONFIG_SIO_PORT);
-    uart_init();
     console_init();
   }
 

src/mainboard/amd/mahogany/romstage.c

@@ -91,7 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb7xx_51xx_lpc_init();
 
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
-	uart_init();
 
 	console_init();
 

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -104,7 +104,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb7xx_51xx_lpc_init();
 
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
-	uart_init();
 
 	console_init();
 

src/mainboard/amd/norwich/romstage.c

@@ -70,7 +70,6 @@ void main(unsigned long bist)
 	 */
 	/* If debug. real setup done in chipset init via devicetree.cb. */
 	cs5536_setup_onchipuart(1);
-	uart_init();
 	console_init();
 
 	/* Halt if there was a built in self test failure */

src/mainboard/amd/persimmon/romstage.c

@@ -53,7 +53,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
     post_code(0x31);
     f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-    uart_init();
     console_init();
   }
 	//reg8 = pmio_read(0x24);

src/mainboard/amd/pistachio/romstage.c

@@ -89,7 +89,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* Pistachio used a FPGA to enable serial debug instead of a SIO
 	 * and it doesn't require any special setup. */
-	uart_init();
 
 	console_init();
 

src/mainboard/amd/rumba/romstage.c

@@ -39,7 +39,6 @@ void main(unsigned long bist)
 	SystemPreInit();
 
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	uart_init();
 	console_init();
 
 	cs5536_early_setup();

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -131,7 +131,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        uart_init();
         console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -212,9 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x32);
 
 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	uart_init();
 	console_init();
-	printk(BIOS_DEBUG, "\n");
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -103,7 +103,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb7xx_51xx_lpc_init();
 
 	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
-	uart_init();
 
 	console_init();