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UPSTREAM: nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17192
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6
Reviewed-on: https://chromium-review.googlesource.com/407194
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Elyes HAOUAS 2016-10-30 18:39:53 +01:00 • committed by chrome-bot
commit 428873a5aa
1 changed files with 6 additions and 6 deletions
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12
src/northbridge/intel/i945/early_init.c
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@ -90,9 +90,9 @@ static void i945m_detect_chipset(void)
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
#endif
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC))
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
}
static void i945_detect_chipset(void)
@ -139,9 +139,9 @@ static void i945_detect_chipset(void)
printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
#endif
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
}
static void i945_setup_bars(void)