From 421c2e5ba44f1693f8b3c869289fc93ab9ef5965 Mon Sep 17 00:00:00 2001 From: huang lin Date: Thu, 16 Oct 2014 09:27:31 -0700 Subject: [PATCH] rk3288: config l2ctlr in romstage Data RAM write latency: 2 cycles Data RAM read latency: 2 cycles Data RAM setup latency: 1 cycle Tag RAM write latency: 1 cycle Tag RAM read latency: 1 cycle Tag RAM setup latency: 1 cycle BUG=None TEST=Boot Veyron Pinky Change-Id: Ic9c909b7913d434bd40016c6a820ddff7e991634 Signed-off-by: huang lin Reviewed-on: https://chromium-review.googlesource.com/223713 Reviewed-by: Doug Anderson Commit-Queue: Doug Anderson --- src/mainboard/google/veyron_pinky/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 714a5c492a..67b2527a96 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -54,6 +54,25 @@ static void regulate_vdd_log(unsigned int mv) pwm_init(1, period_ns, duty_ns); } +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + void main(void) { void *entry; @@ -66,6 +85,7 @@ void main(void) #endif console_init(); + configure_l2ctlr(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200);