veyron_rialto: Make it compile in the firmware branch

This patch does a few things:
- write32() -> writel()
- Adds config files for Rialto
- No program_loading.h in FW branch
- No run_ramstage in FW branch, use older stage_exit() instead
- Kconfig stuff:
  CONSOLE_SERIAL_UART -> DRIVERS_UART
  BOARD_ID_SUPPORT -> BOARD_ID_AUTO
  MAINBOARD_HAS_CHROMEOS -> MAINBOARD_HAS_BOOTBLOCK_INIT
  Added RETURN_FROM_VERSTAGE - selected with rk3288 in toT
  Added ELOG - selected along with CHROMEOS in ToT
  Set VBOOT_*_INDEX - Set in .config files in ToT

Except for the actual board differences, this should look a lot
like other non-laptop veyrons in the firmware branch.

BUG=chrome-os-partner:46150
BRANCH=firmware-veyron
TEST=built and booted on Rialto

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I446bde4f074ffe943a78ddcb0e979c0ffa5a1036
Reviewed-on: https://chromium-review.googlesource.com/304108
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

configs/config.veyron_rialto

@@ -0,0 +1,7 @@
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_VEYRON_RIALTO=y
+CONFIG_CBFS_SIZE=0x100000
+# CONFIG_CONSOLE_SERIAL is not set
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_VBOOT2_VERIFY_FIRMWARE=y

configs/fwserial.veyron_rialto

@@ -0,0 +1 @@
+CONFIG_CONSOLE_SERIAL=y

src/mainboard/google/Kconfig

@@ -297,6 +297,14 @@ config BOARD_GOOGLE_VEYRON_PINKY
 	  Veyron_Pinky is a Chrome OS mainboard.
 	  Veyron_Pinky is based on the Rockchip RK3288 platform.
 
+config BOARD_GOOGLE_VEYRON_RIALTO
+	bool "Veyron_Rialto"
+	help
+	  Google Veyron_Rialto mainboard
+	  Enable this config to select the Google Veyron_Rialto mainboard.
+	  Veyron_Rialto is a Chrome OS mainboard.
+	  Veyron_Rialto is based on the Rockchip RK3288 platform.
+
 config BOARD_GOOGLE_VEYRON_ROMY
 	bool "Veyron_Romy"
 	help
@@ -355,6 +363,7 @@ source "src/mainboard/google/veyron_mickey/Kconfig"
 source "src/mainboard/google/veyron_mighty/Kconfig"
 source "src/mainboard/google/veyron_nicky/Kconfig"
 source "src/mainboard/google/veyron_pinky/Kconfig"
+source "src/mainboard/google/veyron_rialto/Kconfig"
 source "src/mainboard/google/veyron_romy/Kconfig"
 source "src/mainboard/google/veyron_speedy/Kconfig"
 source "src/mainboard/google/veyron_minnie/Kconfig"

src/mainboard/google/veyron_rialto/Kconfig

@@ -21,15 +21,18 @@ if BOARD_GOOGLE_VEYRON_RIALTO
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select BOARD_ID_AUTO
+	select BOARD_ID_SUPPORT
 	select BOARD_ROMSIZE_KB_4096
+	select CHROMEOS
 	select CHROMEOS_VBNV_FLASH
 	select COMMON_CBFS_SPI_WRAPPER
+	select ELOG
 	select HAVE_HARD_RESET
 	select MAINBOARD_DO_NATIVE_VGA_INIT
-	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_BOOTBLOCK_INIT
 	select PHYSICAL_REC_SWITCH
 	select RAM_CODE_SUPPORT
+	select RETURN_FROM_VERSTAGE
 	select SOC_ROCKCHIP_RK3288
 	select SPI_FLASH
 	select SPI_FLASH_GIGADEVICE
@@ -48,9 +51,20 @@ config MAINBOARD_VENDOR
 	string
 	default "Google"
 
+# The 'ecrwhash' is removed from FMAP on Rialto, since we don't have EC.
+# As a result, we have to hack RAMSTAGE and ROMSTAGE index until there are
+# better approaches for vboot2 to find right index.
+config VBOOT_RAMSTAGE_INDEX
+	hex
+	default 0x2
+
+config VBOOT_ROMSTAGE_INDEX
+	hex
+	default 0x1
+
 config BOOT_MEDIA_SPI_BUS
-	int
-	default 2
+        hex
+        default 2
 
 config DRIVER_TPM_I2C_BUS
 	hex
@@ -62,7 +76,7 @@ config DRIVER_TPM_I2C_ADDR
 
 config CONSOLE_SERIAL_UART_ADDRESS
 	hex
-	depends on DRIVERS_UART
+	depends on CONSOLE_SERIAL_UART
 	default 0xFF690000
 
 config PMIC_BUS

src/mainboard/google/veyron_rialto/Kconfig.name

@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_RIALTO
-	bool "Veyron_Rialto"

src/mainboard/google/veyron_rialto/Makefile.inc

@@ -26,7 +26,6 @@ verstage-y += chromeos.c
 verstage-y += reset.c
 
 romstage-y += boardid.c
-romstage-y += chromeos.c
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
 romstage-y += reset.c

src/mainboard/google/veyron_rialto/bootblock.c

@@ -36,9 +36,9 @@
 
 void bootblock_mainboard_early_init()
 {
-	if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
+	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) {
 		assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
-		write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
+		writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
 	}
 
 }
@@ -66,12 +66,12 @@ void bootblock_mainboard_init(void)
 	rkclk_configure_cpu(APLL_1416_MHZ);
 
 	/* i2c1 for tpm */
-	write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
+	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
 	i2c_init(1, 400*KHz);
 
 	/* spi2 for firmware ROM */
-	write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
-	write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
+	writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
+	writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
 	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
 
 	setup_chromeos_gpios();

src/mainboard/google/veyron_rialto/mainboard.c

@@ -48,25 +48,25 @@ static void configure_usb(void)
 
 static void configure_emmc(void)
 {
-	write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
-	write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
-	write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
+	writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
+	writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
+	writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
 
 	gpio_output(GPIO(2, B, 1), 1);		/* EMMC_RST_L */
 }
 
 static void configure_codec(void)
 {
-	write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2);	/* CODEC I2C */
+	writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);	/* CODEC I2C */
 	i2c_init(2, 400*KHz);				/* CODEC I2C */
 
-	write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
-	write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
+	writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
+	writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
 
 	rk808_configure_ldo(6, 1800);	/* VCC18_CODEC */
 
 	/* AUDIO IO domain 1.8V voltage selection */
-	write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
+	writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
 	rkclk_configure_i2s(12288000);
 }
 

src/mainboard/google/veyron_rialto/romstage.c

@@ -27,7 +27,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>
-#include <program_loading.h>
 #include <soc/sdram.h>
 #include <soc/clock.h>
 #include <soc/pwm.h>
@@ -49,7 +48,7 @@ static void regulate_vdd_log(unsigned int mv)
 	const u32 max_regulator_mv = 1350;	/* 1.35V */
 	const u32 min_regulator_mv = 870;	/* 0.87V */
 
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
+	writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
 
 	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
 
@@ -86,6 +85,8 @@ static void sdmmc_power_off(void)
 
 void main(void)
 {
+	void *entry;
+
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
@@ -112,5 +113,18 @@ void main(void)
 
 	cbmem_initialize_empty();
 
-	run_ramstage();
+	entry = vboot2_load_ramstage();
+
+	if (entry == NULL) {
+		timestamp_add_now(TS_START_COPYRAM);
+		entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+					CONFIG_CBFS_PREFIX "/ramstage");
+		timestamp_add_now(TS_END_COPYRAM);
+		if (entry == (void *)-1)
+			die("failed to load ramstage\n");
+	}
+
+	timestamp_add_now(TS_END_ROMSTAGE);
+
+	stage_exit(entry);
 }

src/mainboard/google/veyron_rialto/sdram_configs.c

@@ -42,6 +42,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 1110 */
 #include "sdram_inf/sdram-unused.inc"			/* ram_code = 1111 */
 };
+_Static_assert(ARRAY_SIZE(sdram_configs) == 16, "Must have 16 sdram_configs!");
 
 const struct rk3288_sdram_params *get_sdram_config()
 {