From 40b62ff6c4847279aea885afd3f138aeb2915483 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 22 Apr 2025 11:28:19 -0700 Subject: [PATCH] mb/intel/ptlrvp: Add memory configuration support for T4 LP5 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces support for the T4 LP5 board memory configuration within the ptlrvp mainboard. The addition includes defining the specific memory configurations such as data and strobe signal mappings, early command training, and memory part ID assignments. By implementing these changes, compatibility and functionality are ensured for systems using the T4 LP5 board. The memory configuration is specified for LP5 type memory with detailed DQ and DQS mapping for different DDR channels. This facilitates accurate signal routing and memory initialization. Additionally, updates to associated Makefiles and documentation files reflect these new memory parts (Hynix H58G56BK8BX068) and their IDs, ensuring proper recognition and usage during system builds. BUG=none TEST=Build and verify system initialization on the T4 LP5 board with the updated memory configuration. Confirm that memory training and setup proceed correctly with the newly supported memory part. Change-Id: Ia6e862af8c322fe4467465557c416d4171796e83 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/87422 Reviewed-by: Wonkyu Kim Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- .../intel/ptlrvp/variants/ptlrvp/memory.c | 65 ++++++++++++++++++- .../ptlrvp/variants/ptlrvp/memory/Makefile.mk | 1 + .../ptlrvp/memory/dram_id.generated.txt | 1 + .../variants/ptlrvp/memory/mem_parts_used.txt | 1 + 4 files changed, 66 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c index 6a1706fe9f..350405dc29 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c @@ -65,7 +65,7 @@ static const struct mb_cfg gcs_mem_config = { }, }; -static const struct mb_cfg lp5_mem_config = { +static const struct mb_cfg lp5_t3_mem_config = { .type = MEM_TYPE_LP5X, .lpx_dq_map = { @@ -125,6 +125,66 @@ static const struct mb_cfg lp5_mem_config = { }, }; +static const struct mb_cfg lp5_t4_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 10, 8, 11, 9, 15, 12, 14, 13 }, + .dq1 = { 6, 7, 5, 4, 3, 1, 0, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 0, 3, 2, 7, 6, 5, 4 }, + .dq1 = { 14, 13, 12, 15, 11, 9, 8, 10 }, + }, + .ddr2 = { + .dq0 = { 13, 14, 12, 15, 8, 10, 9, 11 }, + .dq1 = { 6, 7, 5, 4, 1, 3, 2, 0 }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 3, 2, 0, 1 }, + .dq1 = { 14, 13, 12, 15, 11, 9, 8, 10 }, + }, + .ddr4 = { + .dq0 = { 10, 8, 9, 11, 13, 12, 14, 15 }, + .dq1 = { 1, 3, 0, 2, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 1, 0, 2, 3, 7, 6, 5, 4 }, + .dq1 = { 10, 8, 11, 9, 13, 12, 14, 15 }, + }, + .ddr6 = { + .dq0 = { 10, 8, 11, 9, 13, 12, 14, 15 }, + .dq1 = { 6, 5, 7, 4, 0, 1, 2, 3 }, + }, + .ddr7 = { + .dq0 = { 1, 0, 2, 3, 7, 4, 6, 5 }, + .dq1 = { 14, 13, 15, 12, 10, 11, 9, 8 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + static const struct mb_cfg ddr5_mem_config = { .type = MEM_TYPE_DDR5, @@ -149,8 +209,9 @@ const struct mb_cfg *variant_memory_params(void) switch (board_id) { case PTLP_LP5_T3_RVP: + return &lp5_t3_mem_config; case PTLP_LP5_T4_RVP: - return &lp5_mem_config; + return &lp5_t4_mem_config; case GCS_32GB: case GCS_64GB: return &gcs_mem_config; diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk index 1a93597f4e..5575815d1b 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk @@ -6,3 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068 SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 1(0b0001) Parts = H58G66BK8BX067 +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56BK8BX068 diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt index 7f7236d0ec..244c063804 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt @@ -6,3 +6,4 @@ DRAM Part Name ID to assign H58G56BK7BX068 0 (0000) H58G66BK8BX067 1 (0001) +H58G56BK8BX068 2 (0010) diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt index 86a6e201d7..98255ad4d3 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt @@ -11,3 +11,4 @@ # Part Name H58G56BK7BX068 H58G66BK8BX067 +H58G56BK8BX068