From 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 30 Oct 2013 17:54:16 -0700 Subject: [PATCH] tegra124: add CLK_X definitions BUG=None TEST=builds BRANCH=None Change-Id: I163730e45cc18f125e32a1b4c5a685b3a1861486 Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/175220 Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich Reviewed-by: David Hendricks --- src/soc/nvidia/tegra124/include/soc/clock.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 675fbfb4f2..74f29a1cad 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -142,7 +142,22 @@ enum { CLK_W_DVFS = 0x1 << 27, CLK_W_XUSB_SS = 0x1 << 28, CLK_W_MC1 = 0x1 << 30, - CLK_W_EMC1 = 0x1 << 31 + CLK_W_EMC1 = 0x1 << 31, + + CLK_X_AMX1 = 0x1 << 25, + CLK_X_GPU = 0x1 << 24, + CLK_X_SOR0 = 0x1 << 22, + CLK_X_DPAUX = 0x1 << 21, + CLK_X_ADX1 = 0x1 << 20, + CLK_X_VIC = 0x1 << 18, + CLK_X_CLK72MHZ = 0x1 << 17, + CLK_X_HDMI_AUDIO = 0x1 << 16, + CLK_X_EMC_DLL = 0x1 << 14, + CLK_X_VIM2_CLK = 0x1 << 11, + CLK_X_I2C6 = 0x1 << 6, + CLK_X_CAM_MCLK2 = 0x1 << 5, + CLK_X_CAM_MCLK = 0x1 << 4, + CLK_X_SPARE = 0x1 << 0, }; /* PLL stabilization delay in usec */