From 3ecaf04dad1bc5cec11ef9367fc9fc9992dc5e52 Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Tue, 13 May 2025 13:28:54 +0800
Subject: [PATCH] mb/var/uldrenite: Use VBT with limited resolution for 4GBx32
 memory

To have the best usage case on 4GBx32 memory sku, the external display
resolution must not exceed 2560x1700. So use the GPP_E13 signal level
to determine x32 memory configuration and apply the corresponding VBT
accordingly.

BUG=b:415850768
TEST=Check the log for the string "Use vbt-uldrenite_x32mem.bin"

Cq-Depend: chrome-internal:8258325
Change-Id: I82a7415b4c99de9278e04f07a9efb0dfa0bf753d
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87654
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/brya/Kconfig               |  1 +
 .../google/brya/variants/uldrenite/variant.c    | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 59895cc839..07bbec852e 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -697,6 +697,7 @@ config BOARD_GOOGLE_ULDRENITE
 	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
+	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c
index a7927eb0d3..8f1a016fde 100644
--- a/src/mainboard/google/brya/variants/uldrenite/variant.c
+++ b/src/mainboard/google/brya/variants/uldrenite/variant.c
@@ -5,7 +5,9 @@
 #include <boardid.h>
 #include <console/console.h>
 #include <delay.h>
+#include <drivers/intel/gma/opregion.h>
 #include <fw_config.h>
+#include <gpio.h>
 #include <sar.h>
 #include <soc/bootblock.h>
 #include <stdlib.h>
@@ -172,6 +174,21 @@ void variant_update_descriptor(void)
 	}
 }
 
+const char *mainboard_vbt_filename(void)
+{
+	/*
+	 * GPP_E13 High -> One RAM Chip
+	 * GPP_E13 Low  -> Two RAM Chips
+	 */
+	if (gpio_get(GPP_E13)) {
+		printk(BIOS_INFO,
+			"x32 memory detected, so use vbt-uldrenite_x32mem.bin\n");
+		return "vbt-uldrenite_x32mem.bin";
+	}
+	printk(BIOS_INFO, "Non-x32 memory detected, so use vbt.bin\n");
+	return "vbt.bin";
+}
+
 void variant_configure_pads(void)
 {
 	const struct pad_config *base_pads;