diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
index 735197a3bf..ffe692d282 100644
--- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
+++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/intel/xeon_sp/acpi/iiostack.asl>
+#include <soc/acpi.h>
+
 #define MAKE_IIO_DEV(id,rt,pxm)						\
 	Device (PC##id)							\
 	{								\
@@ -25,50 +28,14 @@
 			}						\
 			Return (\_SB_.PR##rt)				\
 		}							\
-		Name (SUPP, 0x00)					\
-		Name (CTRL, 0x00)					\
 		Name (_PXM, pxm)  /* _PXM: Device Proximity */		\
 		Method (_OSC, 4, NotSerialized)				\
 		{							\
-			CreateDWordField (Arg3, 0x00, CDW1)		\
-			If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))  \
-			{							\
-				If (Arg2 < 0x03)				\
-				{						\
-					CDW1 |= 0x02 /* Unknown failure */	\
-					Return (Arg3)				\
-				}						\
-				CreateDWordField (Arg3, 0x04, CDW2)		\
-				CreateDWordField (Arg3, 0x08, CDW3)		\
-				SUPP = CDW2					\
-				CTRL = CDW3					\
-				If ((SUPP & 0x16) != 0x16)		\
-				{						\
-					CTRL &= 0x1E				\
-				}						\
-				/* Never allow SHPC (no SHPC controller in system) */ \
-				CTRL &= 0x1D					\
-				/* Disable Native PCIe AER handling from OS */	\
-				CTRL &= 0x17					\
-				If ((Arg1 != 1)) /* unknown revision */	\
-				{						\
-					CDW1 |= 0x08				\
-				}						\
-				If ((CDW3 != CTRL)) /* capabilities bits were masked */ \
-				{						\
-					CDW1 |= 0x10				\
-				}						\
-				CDW3 = CTRL					\
-				Return (Arg3)					\
-			}							\
-			Else							\
-			{							\
-				/* indicate unrecognized UUID */		\
-				CDW1 |= 0x04					\
-				DBG0 = 0xEE					\
-				Return (Arg3)					\
-			}							\
-		}								\
+			Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,	\
+				(PCIE_CAP_STRUCTURE_CONTROL|		\
+				PCIE_PME_CONTROL|			\
+				PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))	\
+		}							\
 	}
 
 // Keep in sync with iio_domain_set_acpi_name()!
diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
index 7676a3fc37..bf027663e0 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
@@ -36,63 +36,12 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK))
 	{
 		Return (\_SB.PRTID)
 	}
-	Name (SUPP, 0x00) // PCI _OSC Support Field Value
-	Name (CTRL, 0x00) // PCI _OSC Control Field Value
-	Name (SUPC, 0x00) // CXL _OSC Support Field Value
-	Name (CTRC, 0x00) // CXL _OSC Control Field Value
-	Name (_PXM, 0x00)  /* _PXM: Device Proximity */
 	Method (_OSC, 4, NotSerialized)
 	{
-		CreateDWordField (Arg3, 0x00, CDW1)
-		If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */
-			|| Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */
-		{
-			If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */
-			{
-				CDW1 |= 0x02 /* Unknown failure */
-				Return (Arg3)
-			}
-			CreateDWordField (Arg3, 0x04, CDW2)
-			CreateDWordField (Arg3, 0x08, CDW3)
-
-			SUPP = CDW2
-			CTRL = CDW3
-			If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */
-			{
-				CreateDWordField (Arg3, 0x0C, CDW4)
-				CreateDWordField (Arg3, 0x10, CDW5)
-				SUPC = CDW4
-				CTRC = CDW5
-			}
-			If (SUPP & 0x16 != 0x16)
-			{
-				CTRL &= 0x1E
-			}
-			/* Never allow SHPC (no SHPC controller in system) */
-			CTRL &= 0x1D
-			/* Disable Native PCIe AER handling from OS */
-			CTRL &= 0x17
-			If (Arg1 != 1) /* unknown revision */
-			{
-				CDW1 |= 0x08
-			}
-			If (CDW3 != CTRL) /* capabilities bits were masked */
-			{
-				CDW1 |= 0x10
-			}
-			CDW3 = CTRL
-			If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */
-			{
-				CDW5 = CTRC
-			}
-			Return (Arg3)
-		}
-		Else
-		{
-			/* indicate unrecognized UUID */
-			CDW1 |= 0x04
-			IO80 = 0xEE
-			Return (Arg3)
-		}
+		Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,
+			(PCIE_CAP_STRUCTURE_CONTROL|
+			PCIE_PME_CONTROL|
+			PCIE_NATIVE_HOTPLUG_CONTROL), 1,
+			CXL_ERROR_REPORTING_CONTROL))
 	}
 }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
index a2cc03fe17..a81f28a595 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
@@ -32,50 +32,13 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK))
 	{
 		Return (\_SB.PRTID)
 	}
-	Name (SUPP, 0x00)
-	Name (CTRL, 0x00)
 	Name (_PXM, SOCKET)  /* _PXM: Device Proximity */
+
 	Method (_OSC, 4, NotSerialized)
 	{
-		CreateDWordField (Arg3, 0x00, CDW1)
-		If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)
-		{
-			If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */
-			{
-				CDW1 |= 0x02 /* Unknown failure */
-				Return (Arg3)
-			}
-			CreateDWordField (Arg3, 0x04, CDW2)
-			CreateDWordField (Arg3, 0x08, CDW3)
-
-			SUPP = CDW2
-			CTRL = CDW3
-			If (SUPP & 0x16 != 0x16)
-			{
-				CTRL &= 0x1E
-			}
-			/* Never allow SHPC (no SHPC controller in system) */
-			CTRL &= 0x1D
-			/* Disable Native PCIe AER handling from OS */
-			CTRL &= 0x17
-
-			If (Arg1 != 1) /* unknown revision */
-			{
-				CDW1 |= 0x08
-			}
-			If (CDW3 != CTRL) /* capabilities bits were masked */
-			{
-				CDW1 |= 0x10
-			}
-			CDW3 = CTRL
-			Return (Arg3)
-		}
-		Else
-		{
-			/* indicate unrecognized UUID */
-			CDW1 |= 0x04
-			IO80 = 0xEE
-			Return (Arg3)
-		}
+		Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,
+			(PCIE_CAP_STRUCTURE_CONTROL|
+			PCIE_PME_CONTROL|
+			PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))
 	}
 }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
index f6fbe96f60..ab2c3eb68c 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
@@ -2,6 +2,7 @@
 
 #include <intelblocks/itss.h>
 #include <intelblocks/pcr.h>
+#include <soc/acpi.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
 #include <soc/pcr_ids.h>
@@ -9,6 +10,7 @@
 Scope (\_SB)
 {
 	#include "uncore_irq.asl"
+	#include <soc/intel/xeon_sp/acpi/iiostack.asl>
 
 	// Keep in sync with iio_domain_set_acpi_name()!
 	#define SOCKET 0