From 3ea8f422550ff8672f1b08f81c1bd3791a3096d2 Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quanta.corp-partner.google.com>
Date: Wed, 9 Apr 2025 11:03:32 +0800
Subject: [PATCH] mb/google/nissa/var/dirks: Enable ASPM of RTL8111H

Because the NIC does not enter ASPM L1.2.
Here we add "enable_aspm_l1_2" in overridetree for RTL8111H.

BUG=b:407469351
TEST=emerge and test with command powerd_dbus_suspend.
Check firmware log output
[INFO ]  rtl: Enable ASPM L1.2

Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/mainboard/google/brya/variants/dirks/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb
index 27de59cc50..d80ddc488c 100644
--- a/src/mainboard/google/brya/variants/dirks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb
@@ -233,6 +233,7 @@ chip soc/intel/alderlake
 				register "customized_leds" = "0x05af"
 				register "wake" = "GPE0_DW2_14"	# GPP_F14
 				register "device_index" = "0"
+				register "enable_aspm_l1_2" = "1"
 				register "add_acpi_dma_property" = "true"
 				device pci 00.0 on end
 			end