From 3d3e075af56ef81e446529f5efdcb9507d91d4e0 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 30 Jul 2014 13:57:45 -0700 Subject: [PATCH] pearlvalley: Add mainboard for Broadwell Y CRB This is a quick port from wtm2 to test on the broadwell Y CRB. Note that it produces an 8MB image and yet the board has a 16MB SPI flash part. The build tools are not ready to handle a 16MB image yet so just add 8MB of FFs to the end for now. BUG=chrome-os-partner:28234 TEST=boot on pearl valley Change-Id: I849075fc07fa017b5ccca17d0736342a1518db7d Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/210661 Reviewed-by: Aaron Durbin --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/pearlvalley/Kconfig | 47 ++++ src/mainboard/intel/pearlvalley/Makefile.inc | 26 ++ .../intel/pearlvalley/acpi/chromeos.asl | 24 ++ src/mainboard/intel/pearlvalley/acpi/ec.asl | 37 +++ .../intel/pearlvalley/acpi/mainboard.asl | 28 ++ .../intel/pearlvalley/acpi/platform.asl | 73 ++++++ .../intel/pearlvalley/acpi/superio.asl | 20 ++ .../intel/pearlvalley/acpi/thermal.asl | 247 ++++++++++++++++++ .../intel/pearlvalley/acpi/video.asl | 43 +++ src/mainboard/intel/pearlvalley/acpi_tables.c | 219 ++++++++++++++++ src/mainboard/intel/pearlvalley/chromeos.c | 82 ++++++ src/mainboard/intel/pearlvalley/cmos.layout | 139 ++++++++++ src/mainboard/intel/pearlvalley/devicetree.cb | 79 ++++++ src/mainboard/intel/pearlvalley/dsdt.asl | 64 +++++ src/mainboard/intel/pearlvalley/fadt.c | 50 ++++ src/mainboard/intel/pearlvalley/gpio.h | 124 +++++++++ src/mainboard/intel/pearlvalley/hda_verb.h | 99 +++++++ src/mainboard/intel/pearlvalley/mainboard.c | 154 +++++++++++ src/mainboard/intel/pearlvalley/pei_data.c | 71 +++++ src/mainboard/intel/pearlvalley/romstage.c | 47 ++++ src/mainboard/intel/pearlvalley/smihandler.c | 45 ++++ src/mainboard/intel/pearlvalley/thermal.h | 57 ++++ 23 files changed, 1778 insertions(+) create mode 100644 src/mainboard/intel/pearlvalley/Kconfig create mode 100644 src/mainboard/intel/pearlvalley/Makefile.inc create mode 100644 src/mainboard/intel/pearlvalley/acpi/chromeos.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi/ec.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi/mainboard.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi/platform.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi/superio.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi/thermal.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi/video.asl create mode 100644 src/mainboard/intel/pearlvalley/acpi_tables.c create mode 100644 src/mainboard/intel/pearlvalley/chromeos.c create mode 100644 src/mainboard/intel/pearlvalley/cmos.layout create mode 100644 src/mainboard/intel/pearlvalley/devicetree.cb create mode 100644 src/mainboard/intel/pearlvalley/dsdt.asl create mode 100644 src/mainboard/intel/pearlvalley/fadt.c create mode 100644 src/mainboard/intel/pearlvalley/gpio.h create mode 100644 src/mainboard/intel/pearlvalley/hda_verb.h create mode 100644 src/mainboard/intel/pearlvalley/mainboard.c create mode 100644 src/mainboard/intel/pearlvalley/pei_data.c create mode 100644 src/mainboard/intel/pearlvalley/romstage.c create mode 100644 src/mainboard/intel/pearlvalley/smihandler.c create mode 100644 src/mainboard/intel/pearlvalley/thermal.h diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 61317a20e4..d51f6b4ed8 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -25,6 +25,8 @@ config BOARD_INTEL_WTM2 bool "Whitetip Mountain 2 CRB" config BOARD_INTEL_BAYLEYBAY bool "Bayley Bay CRB" +config BOARD_INTEL_PEARLVALLEY + bool "Pearl Valley CRB" endchoice @@ -39,6 +41,7 @@ source "src/mainboard/intel/truxton/Kconfig" source "src/mainboard/intel/xe7501devkit/Kconfig" source "src/mainboard/intel/wtm2/Kconfig" source "src/mainboard/intel/bayleybay/Kconfig" +source "src/mainboard/intel/pearlvalley/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/intel/pearlvalley/Kconfig b/src/mainboard/intel/pearlvalley/Kconfig new file mode 100644 index 0000000000..c22e330e8b --- /dev/null +++ b/src/mainboard/intel/pearlvalley/Kconfig @@ -0,0 +1,47 @@ +if BOARD_INTEL_PEARLVALLEY + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_BROADWELL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select CHROMEOS + select EXTERNAL_MRC_BLOB + select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB + select MONOTONIC_TIMER_MSR + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x1 + +config VBOOT_REFCODE_INDEX + hex + default 0x2 + +config MAINBOARD_DIR + string + default intel/pearlvalley + +config MAINBOARD_PART_NUMBER + string + default "Pearl Valley CRB" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif diff --git a/src/mainboard/intel/pearlvalley/Makefile.inc b/src/mainboard/intel/pearlvalley/Makefile.inc new file mode 100644 index 0000000000..13a4a35256 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/Makefile.inc @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += pei_data.c +ramstage-y += pei_data.c diff --git a/src/mainboard/intel/pearlvalley/acpi/chromeos.asl b/src/mainboard/intel/pearlvalley/acpi/chromeos.asl new file mode 100644 index 0000000000..4cd6dedf46 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/chromeos.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery + Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer + Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect +}) diff --git a/src/mainboard/intel/pearlvalley/acpi/ec.asl b/src/mainboard/intel/pearlvalley/acpi/ec.asl new file mode 100644 index 0000000000..9ae5951aca --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/ec.asl @@ -0,0 +1,37 @@ +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x03), + ACPR, 1, // AC Power (1=present) + , 2, + CFAN, 1, // CPU Fan (1=on) + , 2, + LIDS, 1, // Lid State (1=open) + , 1, + SPTR, 8, // SMBUS Protocol Register + SSTS, 8, // SMBUS Status Register + SADR, 8, // SMBUS Address Register + SCMD, 8, // SMBUS Command Register + SBFR, 256, // SMBUS Block Buffer + SCNT, 8, // SMBUS Block Count + + Offset (0x3a), + ECMD, 8, // EC Command Register + + Offset (0x82), + PECL, 8, // PECI fractional (1/64 Celsius) + PECH, 8, // PECI integer (Celsius) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) +} diff --git a/src/mainboard/intel/pearlvalley/acpi/mainboard.asl b/src/mainboard/intel/pearlvalley/acpi/mainboard.asl new file mode 100644 index 0000000000..09cff9aa64 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/intel/pearlvalley/acpi/platform.asl b/src/mainboard/intel/pearlvalley/acpi/platform.asl new file mode 100644 index 0000000000..e0693928fa --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/intel/pearlvalley/acpi/superio.asl b/src/mainboard/intel/pearlvalley/acpi/superio.asl new file mode 100644 index 0000000000..9092a6c79d --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/intel/pearlvalley/acpi/thermal.asl b/src/mainboard/intel/pearlvalley/acpi/thermal.asl new file mode 100644 index 0000000000..27d5105868 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/thermal.asl @@ -0,0 +1,247 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone +#include "../thermal.h" + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 0 seconds + Name (_TZP, 0) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + Return (CTOK (30)) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (FAN4_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN4_THRESHOLD_ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/intel/pearlvalley/acpi/video.asl b/src/mainboard/intel/pearlvalley/acpi/video.asl new file mode 100644 index 0000000000..3ececa912b --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/intel/pearlvalley/acpi_tables.c b/src/mainboard/intel/pearlvalley/acpi_tables.c new file mode 100644 index 0000000000..2aa2857c31 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/acpi_tables.c @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "thermal.h" + +extern const unsigned char AmlCode[]; + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + + /* TPM Present */ + gnvs->tpmp = 0; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/pearlvalley/chromeos.c b/src/mainboard/intel/pearlvalley/chromeos.c new file mode 100644 index 0000000000..7b8e89a39d --- /dev/null +++ b/src/mainboard/intel/pearlvalley/chromeos.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +/* Compile-time settings for developer and recovery mode. */ +#define DEV_MODE_SETTING 0 +#define REC_MODE_SETTING 0 + +#ifndef __PRE_RAM__ +#include + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static void fill_lb_gpio(struct lb_gpio *gpio, int num, + int polarity, const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = num; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + else if (num >= 0) + gpio->value = get_gpio(num); + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", REC_MODE_SETTING); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", DEV_MODE_SETTING); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif + +int get_developer_mode_switch(void) +{ + return DEV_MODE_SETTING; +} + +int get_recovery_mode_switch(void) +{ + return REC_MODE_SETTING; +} + +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/intel/pearlvalley/cmos.layout b/src/mainboard/intel/pearlvalley/cmos.layout new file mode 100644 index 0000000000..afdd3c66ca --- /dev/null +++ b/src/mainboard/intel/pearlvalley/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/pearlvalley/devicetree.cb b/src/mainboard/intel/pearlvalley/devicetree.cb new file mode 100644 index 0000000000..65395e6f14 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/devicetree.cb @@ -0,0 +1,79 @@ +chip soc/intel/broadwell + + # Enable DisplayPort 1 Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable DisplayPort 0 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + register "s0ix_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 on end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end +end diff --git a/src/mainboard/intel/pearlvalley/dsdt.asl b/src/mainboard/intel/pearlvalley/dsdt.asl new file mode 100644 index 0000000000..f8d3caedaa --- /dev/null +++ b/src/mainboard/intel/pearlvalley/dsdt.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include + + // Chipset specific sleep states + #include + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/pearlvalley/fadt.c b/src/mainboard/intel/pearlvalley/fadt.c new file mode 100644 index 0000000000..a8811d2d56 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/fadt.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/pearlvalley/gpio.h b/src/mainboard/intel/pearlvalley/gpio.h new file mode 100644 index 0000000000..7883a3792e --- /dev/null +++ b/src/mainboard/intel/pearlvalley/gpio.h @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_NATIVE, /* 0: UART1_RXD_R */ + PCH_GPIO_NATIVE, /* 1: UART1_TXD_R */ + PCH_GPIO_NATIVE, /* 2: UART1_RST_N_R */ + PCH_GPIO_NATIVE, /* 3: UART1_CTS_N_R */ + PCH_GPIO_NATIVE, /* 4: I2C0_SDA_R */ + PCH_GPIO_NATIVE, /* 5: I2C0_SCL */ + PCH_GPIO_NATIVE, /* 6: I2C1_SDA */ + PCH_GPIO_NATIVE, /* 7: I2C1_SCL */ + PCH_GPIO_INPUT, /* 8: M.2_WLAN_WAKE_CTRL_N */ + PCH_GPIO_INPUT, /* 9: M.2_BT_UART_WAKE_N */ + PCH_GPIO_INPUT, /* 10: M.2_WWAN_RSVD_WAKE_N */ + PCH_GPIO_UNUSED, /* 11: PCH_GPIO11 / BT_DEV_WAKE */ + PCH_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ + PCH_GPIO_OUT_HIGH, /* 13: LAN_PWREN_N */ + PCH_GPIO_IRQ_EDGE, /* 14: SENSOR_HUB_INT_R_N */ + PCH_GPIO_OUT_HIGH, /* 15: USB32_P0_PWREN_R */ + PCH_GPIO_OUT_LOW, /* 16: LAN_RST_N */ + PCH_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ + PCH_GPIO_NATIVE, /* 18: CLK_REQ_P0_SLOT3_R_N */ + PCH_GPIO_NATIVE, /* 19: CLK_REQ_P1 */ + PCH_GPIO_NATIVE, /* 20: CLK_REQ_P2_M.2_WLAN_R_N */ + PCH_GPIO_NATIVE, /* 21: CLK_REQ_P3_SLOT2_R_N */ + PCH_GPIO_NATIVE, /* 22: CLK_REQ_P4_SLOT1_LAN_N */ + PCH_GPIO_NATIVE, /* 23: CLK_REQ_P5_M.2_SSD_FLEX_R_N */ + PCH_GPIO_OUT_LOW, /* 24: M.2_WWAN_DISABLE_N_ME_LED */ + PCH_GPIO_INPUT, /* 25: USB_WAKEOUT_INTRUDET_N */ + PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ + PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ + PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ + PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ + PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ + PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */ + PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */ + PCH_GPIO_NATIVE, /* 33: SATA3_PHYSLP */ + PCH_GPIO_INPUT, /* 34: SATA_ESATA_ODD_PRSNT_R_N */ + PCH_GPIO_NATIVE, /* 35: GP35_SATAPHYPC */ + PCH_GPIO_INPUT, /* 36: M.2_SSD_SATA2_PCIE1_DET_N */ + PCH_GPIO_INPUT, /* 37: M.2_SSD_SATA3_PCIE0_DET_N */ + PCH_GPIO_NATIVE, /* 38: SATA1_PHYSLP_DIRECT */ + PCH_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_R_N */ + PCH_GPIO_NATIVE, /* 40: USB_OC_0_N */ + PCH_GPIO_NATIVE, /* 41: USB_OC_1_3_N */ + PCH_GPIO_NATIVE, /* 42: TP_USB_OC */ + PCH_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN_R */ + PCH_GPIO_OUT_LOW, /* 44: SH_DFU_R */ + PCH_GPIO_INPUT, /* 45: M.2_WLAN_WIFI_WAKE_N */ + PCH_GPIO_OUT_HIGH, /* 46: POWER_BUTTON */ + PCH_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ + PCH_GPIO_OUT_LOW, /* 48: CLK_REQ_PCIE_PWRGD_R */ + PCH_GPIO_INPUT, /* 49: SENSOR_HUB_I2C_WAKE_R */ + PCH_GPIO_IRQ_EDGE, /* 50: EC_HID_INTR */ + PCH_GPIO_INPUT, /* 51: GPIO_51 */ + PCH_GPIO_ACPI_SCI, /* 52: SMC_RUNTIME_SCI_R_N */ + PCH_GPIO_INPUT, /* 53: GNSS_I2C_IRQ_WAKE */ + PCH_GPIO_INPUT, /* 54: GP54_M.2_WWAN_UIM_SIM_DET */ + PCH_GPIO_INPUT, /* 55: CARD_READER_DET_N */ + PCH_GPIO_UNUSED, /* 56: TP_GPIO56 (NO CONNECTION) */ + PCH_GPIO_OUT_HIGH, /* 57: M.2_WWAN_PWREN */ + PCH_GPIO_OUT_LOW, /* 58: WIFI_RF_KILL_SH_PWREN */ + PCH_GPIO_OUT_LOW, /* 59: PCH_BT_RF_KILL_N */ + PCH_GPIO_UNUSED, /* 60: TP_GP60 */ + PCH_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ + PCH_GPIO_NATIVE, /* 62: SUS_CLK_PCH */ + PCH_GPIO_NATIVE, /* 63: SLP_S5_R_N */ + PCH_GPIO_NATIVE, /* 64: M.2_WLAN_SDIO_CLK_R */ + PCH_GPIO_NATIVE, /* 65: M.2_WLAN_SDIO_CMD_R */ + PCH_GPIO_NATIVE, /* 66: M.2_WLAN_SDIO_DAT0_R */ + PCH_GPIO_NATIVE, /* 67: M.2_WLAN_SDIO_DAT1_R */ + PCH_GPIO_NATIVE, /* 68: M.2_WLAN_SDIO_DAT2_R */ + PCH_GPIO_NATIVE, /* 69: M.2_WLAN_SDIO_DAT3_R */ + PCH_GPIO_NATIVE, /* 70: M.2_WLAN_WIFI_PWREN */ + PCH_GPIO_NATIVE, /* 71: MPHY_PWREN */ + PCH_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ + PCH_GPIO_NATIVE, /* 73: PCH_NOT_N */ + PCH_GPIO_NATIVE, /* 74: SML1_DATA */ + PCH_GPIO_NATIVE, /* 75: SML1_CLK */ + PCH_GPIO_NATIVE, /* 76: GP76_USB3MPHYPC */ + PCH_GPIO_OUT_LOW, /* 77: M.2_WIFI_RST_N */ + PCH_GPIO_INPUT, /* 78: EXTTS_SNI_DRV0_PCH */ + PCH_GPIO_IRQ_EDGE, /* 79: TP_GPIO79 */ + PCH_GPIO_INPUT, /* 80: EXTTS_SNI_DRV1_PCH */ + PCH_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ + PCH_GPIO_NATIVE, /* 82: H_RCIN_N */ + PCH_GPIO_NATIVE, /* 83: GSPI0_CS_R_N */ + PCH_GPIO_NATIVE, /* 84: GSPI0_CLK_R */ + PCH_GPIO_NATIVE, /* 85: GSPI0_MISO_R */ + PCH_GPIO_NATIVE, /* 86: GSPI0_MOSI_BBS0_R */ + PCH_GPIO_OUT_HIGH, /* 87: GSPI1_CS_R_N / TOUCH_PNL_PWREN */ + PCH_GPIO_NATIVE, /* 88: GSPI1_CLK_R */ + PCH_GPIO_OUT_LOW, /* 89: GSPI1_MISO_R / TOUCH_PANEL_RST_N */ + PCH_GPIO_OUT_HIGH, /* 90: GSPI1_MOSI_R / SATA1_PWR_EN */ + PCH_GPIO_NATIVE, /* 91: UART0_RXD */ + PCH_GPIO_NATIVE, /* 92: UART0_TXD */ + PCH_GPIO_NATIVE, /* 93: UART0_RTS_N */ + PCH_GPIO_NATIVE, /* 94: UART0_CTS_N */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/intel/pearlvalley/hda_verb.h b/src/mainboard/intel/pearlvalley/hda_verb.h new file mode 100644 index 0000000000..c34d0f57c7 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/hda_verb.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 + 0x10134210, // Subsystem ID + 0x00000007, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */ + 0x00172010, + 0x00172142, + 0x00172213, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */ + 0x00571cf0, + 0x00571d20, + 0x00571e21, + 0x00571f02, + + /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */ + 0x00671c10, + 0x00671d00, + 0x00671e17, + 0x00671f90, + + /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */ + 0x00771cf0, + 0x00771d20, + 0x00771ea1, + 0x00771f02, + + /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */ + 0x00871c37, + 0x00871d00, + 0x00871ea7, + 0x00871f77, + + /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */ + 0x00971c3e, + 0x00971d00, + 0x00971ea6, + 0x00971f77, + + /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */ + 0x00a71cf0, + 0x00a71d10, + 0x00a71e45, + 0x00a71f43, + + /* coreboot specific header */ + 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x00172001, + 0x00172101, + 0x00172286, + 0x00172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + diff --git a/src/mainboard/intel/pearlvalley/mainboard.c b/src/mainboard/intel/pearlvalley/mainboard.c new file mode 100644 index 0000000000..86182d8450 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/mainboard.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +#include +#endif +#include +#include +#include +#include +#include +#include "hda_verb.h" + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +/* Audio Setup */ + +extern const u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/intel/pearlvalley/pei_data.c b/src/mainboard/intel/pearlvalley/pei_data.c new file mode 100644 index 0000000000..7def002414 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/pei_data.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map for Samus board */ + const u8 dq_map[2][6][2] = { + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; + /* DQS CPU<>DRAM map for Samus board */ + const u8 dqs_map[2][8] = { + { 2, 0, 3, 1, 5, 7, 6, 4 }, + { 3, 1, 2, 0, 6, 4, 5, 7 } }; + + /* One installed DIMM per channel */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + + pei_data->spd_addresses[0] = 0xa2; + pei_data->spd_addresses[2] = 0xa2; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + + pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 1, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 2, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 3, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 4, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 5, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/intel/pearlvalley/romstage.c b/src/mainboard/intel/pearlvalley/romstage.c new file mode 100644 index 0000000000..c7b5da8e8a --- /dev/null +++ b/src/mainboard/intel/pearlvalley/romstage.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "gpio.h" + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data pei_data; + + post_code(0x31); + + printk(BIOS_INFO, "MLB: Intel Pearl Valley CRB\n"); + + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + + /* Fill out PEI DATA */ + memset(&pei_data, 0, sizeof(pei_data)); + mainboard_fill_pei_data(&pei_data); + rp->pei_data = &pei_data; + + romstage_common(rp); +} diff --git a/src/mainboard/intel/pearlvalley/smihandler.c b/src/mainboard/intel/pearlvalley/smihandler.c new file mode 100644 index 0000000000..bec0b615f1 --- /dev/null +++ b/src/mainboard/intel/pearlvalley/smihandler.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/intel/pearlvalley/thermal.h b/src/mainboard/intel/pearlvalley/thermal.h new file mode 100644 index 0000000000..ce48c6148b --- /dev/null +++ b/src/mainboard/intel/pearlvalley/thermal.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 48 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x40 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 52 +#define FAN2_THRESHOLD_ON 64 +#define FAN2_PWM 0x80 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 60 +#define FAN1_THRESHOLD_ON 68 +#define FAN1_PWM 0xb0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 66 +#define FAN0_THRESHOLD_ON 78 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif