From 3c1b142b4da0ebd43ece40fcd4ae999fe6a5c4eb Mon Sep 17 00:00:00 2001 From: Barnali Sarkar Date: Tue, 10 Jan 2017 22:09:00 +0530 Subject: [PATCH] UPSTREAM: soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1 As per Audio PCH team recommendation the iDisplay Audio/SDIN2 should be disabled to bypass InitializeDisplayAudio() function call. Display Audio Codec is HDA-Link Codec, which is not supported in I2S mode BUG=chrome-os-partner:61548 BRANCH=none TEST=Tested to verify that InitializeDisplayAudio() does not get called. Change-Id: I5900291ca4b2929db3e09277ffc3dce24d8de6fb Signed-off-by: Patrick Georgi Original-Commit-Id: 32997fb0bcb9f4183789331a91fd83138776b96f Original-Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499 Original-Signed-off-by: Barnali Sarkar Original-Reviewed-on: https://review.coreboot.org/18091 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/430611 Commit-Ready: Aaron Durbin Tested-by: Aaron Durbin Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/chip_fsp20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2aef65af29..ebd31349d8 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -190,6 +190,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchIshEnable = config->IshEnable; params->PchHdaEnable = config->EnableAzalia; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; + params->PchHdaIDispCodecDisconnect = 1; params->PchHdaDspEnable = config->DspEnable; params->XdciEnable = config->XdciEnable; params->Device4Enable = config->Device4Enable;