From 3c17eef012dd35496076a371d58629aacf3168e4 Mon Sep 17 00:00:00 2001 From: Vaibhav Shankar Date: Wed, 14 Sep 2016 10:39:29 -0700 Subject: [PATCH] UPSTREAM: mainboard/google/reef: Configure PERST_0 pin This configures PERST_0 in devicetree. For boards without PERST_0, the pin should be disabled. For boards with PERST_0 the correct GPIO needs to be assigned. BUG=chrome-os-partner:55877 BRANCH=None TEST=None Signed-off-by: Vaibhav Shankar Reviewed-on: https://review.coreboot.org/16603 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46 Reviewed-on: https://chromium-review.googlesource.com/385092 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index f15260b2db..c83df61f59 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -12,6 +12,10 @@ chip soc/intel/apollolake register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3.