From 3c17c59bb4e90b013c49c0ef19fff1f6bafba8c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 10 Jun 2016 19:35:15 +0200 Subject: [PATCH] UPSTREAM: arch/riscv: Add misc.c to bootblock/romstage to get udelay() The uart8250mem driver needs it. BUG=None BRANCH=None TEST=None Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db Original-Signed-off-by: Jonathan Neuschfer Original-Reviewed-on: https://review.coreboot.org/15147 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Ronald G. Minnich Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/352024 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/arch/riscv/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 6784d9bb48..4521dcbba6 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -34,6 +34,7 @@ bootblock-y += trap_handler.c bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += rom_media.c +bootblock-y += misc.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -57,6 +58,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c romstage-y += stages.c romstage-y += rom_media.c +romstage-y += misc.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \