From 3c0fe9ef3b6f212b1ac666a182c957a15f0fa2b6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 31 Mar 2025 15:31:57 +0200 Subject: [PATCH] mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutil MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SoC code requires for GPE DW config values to be different. Assign the default values of PMC GPIO_CONF register as GPIO GPEs are not used on this platform. Fixes the assertion in soc/intel/elkhartalke/pmutil. TEST=Boot Protectli VP2420 to Ubuntu 24.04. Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/87049 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/protectli/vault_ehl/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index 10782b265d..0db005f1e8 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -18,9 +18,9 @@ chip soc/intel/elkhartlake # route, i.e., if this route changes then the affected GPE # offset bits also need to be changed. This sets the PMC register # GPE_CFG fields. - #register "pmc_gpe0_dw1" = "PMC_GPE_SCC_63_32" - #register "pmc_gpe0_dw2" = "PMC_GPE_N_31_0" - #register "pmc_gpe0_dw3" = "PMC_GPE_SCC_31_0" + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" register "tcc_offset" = "5" # TCC of 95C