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Fixed .config files (remove arch command)

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Add support for new mainboard and chipset combos
This commit is contained in:
Ronald G. Minnich 2001-10-30 17:22:50 +00:00
commit 3be04423cd
14 changed files with 633 additions and 24 deletions
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32
src/mainboard/gigabit/ga-6oxe/Config Normal file
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@ -0,0 +1,32 @@
arch i386
mainboardinit cpu/i386/entry16.inc
ldscript cpu/i386/entry16.lds
mainboardinit cpu/i386/reset16.inc
ldscript cpu/i386/reset16.lds
mainboardinit superio/ITE/it8712f/setup_serial.inc
mainboardinit pc80/serial.inc
northbridge intel/815ep
southbridge intel/ich2
mainboardinit cpu/p6/earlymtrr.inc
superio ITE/it8712f
# option FLASH_ROM_SIZE=524288
option ENABLE_FIXED_AND_VARIABLE_MTRRS
option NO_KEYBOARD
option HAVE_PIRQ_TABLE
option ZKERNEL_START=0xfffc0000
option ZKERNEL_MASK=0x7f
object mainboard.o
object irq_tables.o
cpu p6
cpu p5

284
src/mainboard/gigabit/ga-6oxe/irq_tables.c Normal file
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#include <subr.h>
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
0x52495024, /* u32 signature */
0x100, /* u16 version */
208, /* u16 size */
0x0, /* u8 rtr_bus - router bus */
0xf8, /* u8 rtr_devfn - router devfn */
0xe20, /* u16 exclusive_irqs - mask of IRQs for PCI use */
0x8086, /* u16 rtr_vendor - router vendor id */
0x7000, /* u16 rtr_devfn - router device id */
0, /* u8 miniport_data - crap */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
19, /* u8 checksum. sum of all bytes mod 256 must be 0
*/
{
/* for each slot.. */
{ /* slot 0 */
0x0, /* u8 bus */
0x10, /* u16 devfn */
{
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x61, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x63, /* link */
0xdeb8, /* bitmap */
},
},
0x1, /* slot */
0x0, /* rfu */
},
{ /* slot 1 */
0x2, /* u8 bus */
0x40, /* u16 devfn */
{
{
0x68, /* link */
0xdeb8, /* bitmap */
},
{
0x69, /* link */
0xdeb8, /* bitmap */
},
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x6b, /* link */
0xdeb8, /* bitmap */
},
},
0x2, /* slot */
0x0, /* rfu */
},
{ /* slot 2 */
0x2, /* u8 bus */
0x0, /* u16 devfn */
{
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x69, /* link */
0xdeb8, /* bitmap */
},
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x60, /* link */
0xdeb8, /* bitmap */
},
},
0x3, /* slot */
0x0, /* rfu */
},
{ /* slot 3 */
0x2, /* u8 bus */
0x8, /* u16 devfn */
{
{
0x69, /* link */
0xdeb8, /* bitmap */
},
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
},
0x4, /* slot */
0x0, /* rfu */
},
{ /* slot 4 */
0x2, /* u8 bus */
0x10, /* u16 devfn */
{
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x69, /* link */
0xdeb8, /* bitmap */
},
},
0x5, /* slot */
0x0, /* rfu */
},
{ /* slot 5 */
0x2, /* u8 bus */
0x18, /* u16 devfn */
{
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x69, /* link */
0xdeb8, /* bitmap */
},
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
},
0x6, /* slot */
0x0, /* rfu */
},
{ /* slot 6 */
0x2, /* u8 bus */
0x20, /* u16 devfn */
{
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x69, /* link */
0xdeb8, /* bitmap */
},
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x60, /* link */
0xdeb8, /* bitmap */
},
},
0x7, /* slot */
0x0, /* rfu */
},
{ /* slot 7 */
0x2, /* u8 bus */
0x28, /* u16 devfn */
{
{
0x69, /* link */
0xdeb8, /* bitmap */
},
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
},
0x8, /* slot */
0x0, /* rfu */
},
{ /* slot 8 */
0x2, /* u8 bus */
0x50, /* u16 devfn */
{
{
0x6a, /* link */
0xdeb8, /* bitmap */
},
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x69, /* link */
0xdeb8, /* bitmap */
},
},
0x9, /* slot */
0x0, /* rfu */
},
{ /* slot 9 */
0x0, /* u8 bus */
0xf8, /* u16 devfn */
{
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x61, /* link */
0xdeb8, /* bitmap */
},
{
0x6b, /* link */
0xdeb8, /* bitmap */
},
{
0x63, /* link */
0xdeb8, /* bitmap */
},
},
0x0, /* slot */
0x0, /* rfu */
},
{ /* slot 10 */
0x0, /* u8 bus */
0x8, /* u16 devfn */
{
{
0x60, /* link */
0xdeb8, /* bitmap */
},
{
0x61, /* link */
0xdeb8, /* bitmap */
},
{
0x62, /* link */
0xdeb8, /* bitmap */
},
{
0x63, /* link */
0xdeb8, /* bitmap */
},
},
0x0, /* slot */
0x0, /* rfu */
},
}
}; /* end of irq routing table */

9
src/mainboard/gigabit/ga-6oxe/mainboard.c Normal file
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@ -0,0 +1,9 @@
#include <printk.h>
#include <pci.h>
#include <cpu/p5/io.h>
void mainboard_fixup()
{
/* TODO : hcyun@etri.re.kr */
}

4
src/northbridge/intel/82815ep/Config Normal file
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@ -0,0 +1,4 @@
raminit northbridge/intel/815ep/raminit.inc
raminit sdram/generic_sdram.inc
object northbridge.o

58
src/northbridge/intel/82815ep/northbridge.c Normal file
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@ -0,0 +1,58 @@
/*
Intel FW82815EP northbridge related...
(c) 2001 HeeChul Yun (hcyun@etri.re.kr)
*/
#include <pci.h>
#include <printk.h>
#define REG_DRP 0x52
#define REG_DRP2 0x54
static int DRP_sizetbl[] = {
0, 32, 32, 48,
64, 64, 96, 128,
128, 128, 128, 192,
256, 256, 256, 512
};
unsigned long sizeram()
{
unsigned long totalmem, curmem;
unsigned char regval;
struct pci_dev *pcidev;
totalmem = 0;
pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
pci_read_config_byte(pcidev, REG_DRP, &regval);
printk_info("DRP0 = 0x%x\n", regval);
curmem = DRP_sizetbl[regval & 0x0F];
printk_info("DIMM0 - size = %ldM\n", curmem);
totalmem += curmem;
curmem = DRP_sizetbl[(regval & 0xF0) >> 8 ];
printk_info("DIMM1 - size = %ldM\n", curmem);
totalmem += curmem;
pci_read_config_byte(pcidev, REG_DRP2, &regval);
printk_info("DRP1 = 0x%x\n", regval);
curmem = DRP_sizetbl[regval & 0x0F];
printk_info("DIMM2 - size = %ldM\n", curmem );
totalmem += curmem;
return totalmem * 1024;
}

230
src/northbridge/intel/82815ep/raminit.inc Normal file
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@ -0,0 +1,230 @@
/*
Intel 815EP MCH sdram initialization
$Revision$
$Author$
$Date$
*/
jmp intel_815_out
#define CS_READ_BYTE(addr) \
movl $addr, %eax ; \
PCI_READ_CONFIG_BYTE
#define CS_WRITE_BYTE(addr, byte) \
movl $addr, %eax ; \
movl $byte, %edx ; \
PCI_WRITE_CONFIG_BYTE
#define CS_WRITE_WORD(addr, word) \
movl $addr, %eax ; \
movl $word, %ecx ; \
PCI_WRITE_CONFIG_WORD
#define CS_WRITE_LONG(addr, dword) \
movl $addr, %eax ; \
movl $dword, %ecx ; \
PCI_WRITE_CONFIG_DWORD
#define FIRST_NORMAL_REFERENCE()
#define SPECIAL_FINISHUP()
#define RAM_COMMAND_NORMAL 0x0 // self refresh
#define RAM_COMMAND_NORMAL_0 0x1 // 15.6 us
#define RAM_COMMAND_NORMAL_1 0x2 // 7.8 us
#define RAM_COMMAND_NORMAL_2 0x3 // 1.28
#define RAM_COMMAND_NOP 0x4
#define RAM_COMMAND_PRECHARGE 0x5
#define RAM_COMMAND_MRS 0x6
#define RAM_COMMAND_CBR 0x7
#define SET_RAM_COMMAND(command) \
movl $REG_DRAMT, %eax ; \
PCI_READ_CONFIG_BYTE ; \
andl $0x1F, %eax ; \
orl $((command) << 5), %eax ; \
movl %eax, %edx ; \
movl $REG_DRAMT, %eax ; \
PCI_WRITE_CONFIG_BYTE
#define ENABLE_REFRESH()
#define REG_PCICMD0 0x04
#define REG_PCICMD1 0x05
#define REG_MCHCFG 0x50
#define REG_DRP 0x52
#define REG_DRAMT 0x53
#define REG_DRP2 0x54
#define REG_FDHC 0x58
#define REG_PAM0 0x59
#define REG_PAM1 0x5A
#define REG_PAM2 0x5B
#define REG_PAM3 0x5C
#define REG_PAM4 0x5D
#define REG_PAM5 0x5E
#define REG_PAM6 0x5F
#define REG_SMRAM 0x70
#define REG_BUFF_SC0 0x92
#define REG_BUFF_SC1 0x93
/* default values for config registers */
ram_set_registers:
CS_WRITE_BYTE(REG_PCICMD1, 0x00) // disable SERR#
CS_READ_BYTE(REG_MCHCFG)
TTYS0_TX_HEX32(%eax)
// CS_WRITE_BYTE(REG_MCHCFG, 0x50)
CS_WRITE_BYTE(REG_DRP, 0x00)
CS_WRITE_BYTE(REG_DRP2, 0x00)
CS_WRITE_BYTE(REG_DRAMT, 0x08)
CS_WRITE_BYTE(REG_FDHC, 0x00)
CS_WRITE_BYTE(REG_PAM0, 0x00)
CS_WRITE_BYTE(REG_PAM1, 0x00)
CS_WRITE_BYTE(REG_PAM2, 0x00)
CS_WRITE_BYTE(REG_PAM3, 0x00)
CS_WRITE_BYTE(REG_PAM4, 0x00)
CS_WRITE_BYTE(REG_PAM5, 0x00)
CS_WRITE_BYTE(REG_PAM6, 0x00)
CS_WRITE_BYTE(REG_SMRAM, 0x00)
CS_WRITE_BYTE(REG_BUFF_SC0, 0xff)
CS_WRITE_BYTE(REG_BUFF_SC1, 0xff)
RET_LABEL(ram_set_registers)
ram_set_spd_registers:
// TODO: SPD
CS_WRITE_BYTE(REG_DRP, 0x0E) // 256M, SS, DIMM0
CS_WRITE_BYTE(REG_DRAMT, 0x00) //
RET_LABEL(ram_set_spd_registers)
ram_enable_1: .string "\r\nRam Enable 1\r\n"
ram_enable_2: .string "\r\nRam Enable 2\r\n"
ram_enable_3: .string "\r\nRam Enable 3\r\n"
ram_enable_4: .string "\r\nRam Enable 4\r\n"
ram_enable_5: .string "\r\nRam Enable 5\r\n"
ram_fail: .string "\r\n--- FAILED TO INITIALIZE \r\n"
ram_pass: .string "\r\n--- SDRAM TEST PASSED \r\n"
#define DO_READ(addr) \
movl addr, %eax ; \
movl (%eax), %ebx
#define DO_WRITE(addr, data) \
movl addr, %eax ; \
movl data, %ebx ; \
movl %ebx, (%eax)
#define IODELAY outb %al, $0x80 // took approximately 1us
mydelay:
mov $2000, %ecx
delay_loop:
IODELAY
decl %ecx
jne delay_loop
RETSP
enable_sdram:
// Enterring NOP command enable mode
TTYS0_TX_STRING($ram_enable_1)
SET_RAM_COMMAND(RAM_COMMAND_NOP)
DO_READ($0x0) // do read from sdram address 0
CALLSP(mydelay) // wait a while (minimal 200us)
// Precharge all
TTYS0_TX_STRING($ram_enable_2)
SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE)
// DO_READ($0x0) // do read from sdram address 0
DO_READ($0x2000)
// 8 auto refresh command / "CAS before RAS"
TTYS0_TX_STRING($ram_enable_3)
SET_RAM_COMMAND(RAM_COMMAND_CBR)
mov $8, %ecx
1:
DO_READ($0x0)
// IODELAY
TTYS0_TX_CHAR($'.')
dec %ecx
jne 1b
// Mode register set
TTYS0_TX_STRING($ram_enable_4)
SET_RAM_COMMAND(RAM_COMMAND_MRS)
/* MAx[14:0] lines,
* MAx[2:0 ] 010 == burst mode of 4
* MAx[3:3 ] 1 == interleave wrap type
* MAx[4:4 ] == CAS# latency bit -> 0=2ns, 1=3ns
* MAx[6:5 ] == 01
* MAx[12:7] == 0
*/
// Get CAS latency
// CAS# =2 clk -> 0x2a -> read 0x150
// CAS# =3 clk -> 0x3a -> read 0x1D0
movl $REG_DRAMT, %eax
PCI_READ_CONFIG_BYTE
andl $0x4, %eax // bit 2 ( 0 = 3clk, 1 = 2ckl )
xorl $0x4, %eax // Inverting bit 2
shll $2, %eax // MA4 = inv(bit 2)
orl $0x2a, %eax
shll $3, %eax
movl (%eax), %ebx // MRS comand.
// TTYS0_TX_HEX32(%eax)
// Normal operation mode
TTYS0_TX_STRING($ram_enable_5)
SET_RAM_COMMAND(RAM_COMMAND_NORMAL_1)
DO_READ($0x0)
DO_WRITE($0x0, $0x0)
#if 0
// Now setup is done. we can write to SDRAM
// test this.
movl $0x0, %esi // addr = 0
movl $0x0, %edi
movl $0x12345678, %edi // data = 0x12345678
// fill
movl %edi, (%esi)
movl %edi, 8(%esi)
movl %edi, 16(%esi)
// verify..
movl (%esi), %edi
TTYS0_TX_HEX32(%edi)
movl 8(%esi), %edi
TTYS0_TX_HEX32(%edi)
movl 16(%esi), %edi
TTYS0_TX_HEX32(%edi)
cmpl $0x12345678, %edi
je pass
fail:
TTYS0_TX_HEX32(%edi)
TTYS0_TX_STRING($ram_fail)
jmp doneDetection
pass:
TTYS0_TX_HEX32(%edi)
TTYS0_TX_STRING($ram_pass)
doneDetection:
#endif // 0
RET_LABEL(enable_sdram)
intel_815_out:

18
util/config/asus_cua_doc.config
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@ -1,15 +1,10 @@
# Sample config file for ASUS CUA with DoC Millennium (as root)
arch i386
# This will make a target directory of ./winfast
target asus_cua
# Asus CUA
mainboard asus/cua
raminit northbridge/acer/m1631/chipset_init.inc
# protected mode startup
option PROTECTED_MODE_STARTUP
# Enable Serial Console for debugging
option SERIAL_CONSOLE
@ -19,20 +14,11 @@ option CONFIGURE_L2_CACHE
# use DOC MIL
option USE_DOC_MIL
docipl northbridge/acer/m1631/ipl.S
# we need to do this for protected=mode DOC
# first we need to fix the internals of docipl command
# addaction ipl.o mv docipl adocipl
# addaction ipl.o dd if=adocipl of=docipl bs=1 skip=1040384
docipl mainboard/asus/cua/ipl.S
# Use the internal VGA frame buffer device
# option HAVE_FRAMEBUFFER
# we don't have PIRQ tables yet.
nooption HAVE_PIRQ_TABLE
# Path to your kernel (vmlinux)
linux ~/src/bios/linux-2.4.0-ali

1
util/config/ds10.config
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@ -1,4 +1,3 @@
arch alpha
# This will make a target directory of ./ds10
# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
# CONFIG TOOL. Make it absolute if you like

2
util/config/l440bx-test12.config
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@ -1,7 +1,5 @@
# This will make a target directory of ./winfast
# Note that this is RELATIVE TO WHERE YOU ARE WHEN YOU RUN THE
# CONFIG TOOL. Make it absolute if you like
arch i386
target /tmp/fbios/l440bx
mainboard intel/l440bx

6
util/config/matsonic.config
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@ -1,5 +1,4 @@
# Sample config file for Matsonic MS7308E with DoC Millennium (as root)
arch i386
# This will make a target directory of ./matsonic
target matsonic
@ -22,3 +21,8 @@ linux /usr/src/linux
# Kernel command line parameters
commandline root=/dev/nftla1 single
# use DOC MIL
option USE_DOC_MIL
docipl northsouthbridge/sis/630/ipl.S

6
util/config/pcchips.config
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@ -1,5 +1,4 @@
# Sample config file for PCCHIPS M810LMR with DoC Millennium (as root)
arch i386
# This will make a target directory of ./pcchips
target pcchips
@ -21,3 +20,8 @@ linux /usr/src/linux
# Kernel command line parameters
commandline root=/dev/hda1 console=ttyS0,115200 console=tty0 single
# use DOC MIL
option USE_DOC_MIL
docipl northsouthbridge/sis/730/ipl.S

1
util/config/sis540.config
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@ -1,5 +1,4 @@
# Sample config file for SiS 550 SoC with DoC Millennium (as root)
arch i386
# This will make a target directory of ./winfast
target sis540

1
util/config/sis550.config
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@ -1,5 +1,4 @@
# Sample config file for SiS 550 SoC with DoC Millennium (as root)
arch i386
# This will make a target directory of ./winfast
target sis550

5
util/config/winfast.config
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@ -1,5 +1,4 @@
# Sample config file for Winfast 6300 with DoC Millennium (as root)
arch i386
# This will make a target directory of ./winfast
target winfast
@ -9,6 +8,10 @@ mainboard leadtek/winfast6300
# Enable Serial Console for debugging
option SERIAL_CONSOLE
# use DOC MIL
option USE_DOC_MIL
docipl northsouthbridge/sis/630/ipl.S
# Enable MicroCode update and L2 Cache init for PII and PIII
option UPDATE_MICROCODE
option CONFIGURE_L2_CACHE