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aarch64: Comment out some parts of code to allow build

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BUG=None
BRANCH=none
TEST=Ran image in foundation model
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>

Change-Id: I8f7a0d5aa8d710a679517811331a21c84732a3ed
Reviewed-on: https://chromium-review.googlesource.com/185274
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
This commit is contained in:
Marcelo Povoa 2014-02-06 15:17:45 -08:00 • committed by chrome-internal-fetch
commit 3bc412c2a0
4 changed files with 12 additions and 92 deletions
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83
src/arch/aarch64/include/arch/io.h
View file

@ -22,7 +22,7 @@
#include <types.h>
#include <arch/byteorder.h>
#include <barrier.h>
#include <arch/barrier.h>
/*
* Generic IO read/write. These perform native-endian accesses.
@ -86,9 +86,9 @@ static inline u64 __raw_readq(const volatile void *addr)
* ordering rules but do not guarantee any ordering relative to Normal memory
* accesses.
*/
#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
#define readb_relaxed(c) ({ u8 __u = __raw_readb(c); __u; })
#define readw_relaxed(c) ({ u16 __u = le16_to_cpu((__force __le16)__raw_readw(c)); __u; })
#define readl_relaxed(c) ({ u32 __u = le32_to_cpu((__force __le32)__raw_readl(c)); __u; })
#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
@ -107,39 +107,6 @@ static inline u64 __raw_readq(const volatile void *addr)
#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
/*
* I/O port access primitives.
*/
static inline u8 inb(unsigned long addr)
{
return readb(addr + CONFIG_PCI_IOBASE);
}
static inline u16 inw(unsigned long addr)
{
return readw(addr + CONFIG_PCI_IOBASE);
}
static inline u32 inl(unsigned long addr)
{
return readl(addr + CONFIG_PCI_IOBASE);
}
static inline void outb(u8 b, unsigned long addr)
{
writeb(b, addr + CONFIG_PCI_IOBASE);
}
static inline void outw(u16 b, unsigned long addr)
{
writew(b, addr + CONFIG_PCI_IOBASE);
}
static inline void outl(u32 b, unsigned long addr)
{
writel(b, addr + CONFIG_PCI_IOBASE);
}
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
@ -148,48 +115,6 @@ static inline void outl(u32 b, unsigned long addr)
#define outw_p(x, addr) outw((x), (addr))
#define outl_p(x, addr) outl((x), (addr))
static inline void insb(unsigned long addr, void *buffer, int count)
{
u8 *buf = buffer;
while (count--)
*buf++ = __raw_readb(addr + CONFIG_PCI_IOBASE);
}
static inline void insw(unsigned long addr, void *buffer, int count)
{
u16 *buf = buffer;
while (count--)
*buf++ = __raw_readw(addr + CONFIG_PCI_IOBASE);
}
static inline void insl(unsigned long addr, void *buffer, int count)
{
u32 *buf = buffer;
while (count--)
*buf++ = __raw_readl(addr + CONFIG_PCI_IOBASE);
}
static inline void outsb(unsigned long addr, const void *buffer, int count)
{
const u8 *buf = buffer;
while (count--)
__raw_writeb(*buf++, addr + CONFIG_PCI_IOBASE);
}
static inline void outsw(unsigned long addr, const void *buffer, int count)
{
const u16 *buf = buffer;
while (count--)
__raw_writew(*buf++, addr + CONFIG_PCI_IOBASE);
}
static inline void outsl(unsigned long addr, const void *buffer, int count)
{
const u32 *buf = buffer;
while (count--)
__raw_writel(*buf++, addr + CONFIG_PCI_IOBASE);
}
#define insb_p(port,to,len) insb(port,to,len)
#define insw_p(port,to,len) insw(port,to,len)
#define insl_p(port,to,len) insl(port,to,len)

4
src/arch/aarch64/include/arch/pci_ops.h
View file

@ -21,5 +21,9 @@
#define ARCH_AARCH64_PCI_OPS_H
/* V8 has PCI in some form. We will need to fill this in. */
static inline const struct pci_bus_operations *pci_config_default(void)
{
return NULL;
}
#endif

10
src/arch/aarch64/tables.c
View file

@ -29,14 +29,6 @@
#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size)
{
printk(BIOS_WARNING,
"WARNING: you need to define get_cbmem_table for your board\n");
*base = 0;
*size = 0;
}
void cbmem_arch_init(void)
{
}
@ -45,8 +37,6 @@ struct lb_memory *write_tables(void)
{
unsigned long table_pointer, new_table_pointer;
cbmem_base_check();
post_code(0x9d);
table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,

7
src/mainboard/emulation/foundation-armv8/timer.c
View file

@ -15,10 +15,11 @@
#include <delay.h>
void udelay(unsigned int n) {
void udelay(unsigned int n)
{
/* TODO provide delay here. */
}
int init_timer(void) {
return 0;
void init_timer(void)
{
}