From 3b700fd42ac5617fc24cdc27329fe1a7e85f3dd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Philipp=20Gro=C3=9F?= Date: Thu, 9 Jan 2025 21:15:26 +0100 Subject: [PATCH] mb/asrock: Add Z87 Extreme3 (Haswell) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - Both rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU) - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) tested: - PCI slots - IR header - COM Port header - PS/2 Mouse/Keyboard Port - Optical SPDIF Out Port Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Signed-off-by: Jan Philipp Groß Reviewed-on: https://review.coreboot.org/c/coreboot/+/85926 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asrock/z87_extreme3/Kconfig | 27 +++ .../asrock/z87_extreme3/Kconfig.name | 4 + src/mainboard/asrock/z87_extreme3/Makefile.mk | 6 + src/mainboard/asrock/z87_extreme3/acpi/ec.asl | 3 + .../asrock/z87_extreme3/acpi/platform.asl | 10 + .../asrock/z87_extreme3/acpi/superio.asl | 3 + .../asrock/z87_extreme3/board_info.txt | 7 + src/mainboard/asrock/z87_extreme3/bootblock.c | 36 ++++ src/mainboard/asrock/z87_extreme3/data.vbt | Bin 0 -> 6144 bytes .../asrock/z87_extreme3/devicetree.cb | 140 +++++++++++++ src/mainboard/asrock/z87_extreme3/dsdt.asl | 26 +++ .../asrock/z87_extreme3/gma-mainboard.ads | 17 ++ src/mainboard/asrock/z87_extreme3/gpio.c | 186 ++++++++++++++++++ src/mainboard/asrock/z87_extreme3/hda_verb.c | 28 +++ src/mainboard/asrock/z87_extreme3/romstage.c | 37 ++++ 15 files changed, 530 insertions(+) create mode 100644 src/mainboard/asrock/z87_extreme3/Kconfig create mode 100644 src/mainboard/asrock/z87_extreme3/Kconfig.name create mode 100644 src/mainboard/asrock/z87_extreme3/Makefile.mk create mode 100644 src/mainboard/asrock/z87_extreme3/acpi/ec.asl create mode 100644 src/mainboard/asrock/z87_extreme3/acpi/platform.asl create mode 100644 src/mainboard/asrock/z87_extreme3/acpi/superio.asl create mode 100644 src/mainboard/asrock/z87_extreme3/board_info.txt create mode 100644 src/mainboard/asrock/z87_extreme3/bootblock.c create mode 100644 src/mainboard/asrock/z87_extreme3/data.vbt create mode 100644 src/mainboard/asrock/z87_extreme3/devicetree.cb create mode 100644 src/mainboard/asrock/z87_extreme3/dsdt.asl create mode 100644 src/mainboard/asrock/z87_extreme3/gma-mainboard.ads create mode 100644 src/mainboard/asrock/z87_extreme3/gpio.c create mode 100644 src/mainboard/asrock/z87_extreme3/hda_verb.c create mode 100644 src/mainboard/asrock/z87_extreme3/romstage.c diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig b/src/mainboard/asrock/z87_extreme3/Kconfig new file mode 100644 index 0000000000..0b03123a7d --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_EXTREME3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_extreme3" + +config MAINBOARD_PART_NUMBER + default "Z87 Extreme3" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB3_0_1 (Upper) + # Header: USB2_3 +endif diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig.name b/src/mainboard/asrock/z87_extreme3/Kconfig.name new file mode 100644 index 0000000000..3b90f10639 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_EXTREME3 + bool "Z87 Extreme3" diff --git a/src/mainboard/asrock/z87_extreme3/Makefile.mk b/src/mainboard/asrock/z87_extreme3/Makefile.mk new file mode 100644 index 0000000000..c3cf55d397 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_extreme3/acpi/ec.asl b/src/mainboard/asrock/z87_extreme3/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme3/acpi/platform.asl b/src/mainboard/asrock/z87_extreme3/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_extreme3/acpi/superio.asl b/src/mainboard/asrock/z87_extreme3/acpi/superio.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme3/board_info.txt b/src/mainboard/asrock/z87_extreme3/board_info.txt new file mode 100644 index 0000000000..6e3ed5896b --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Extreme3/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_extreme3/bootblock.c b/src/mainboard/asrock/z87_extreme3/bootblock.c new file mode 100644 index 0000000000..7a6607c441 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_extreme3/data.vbt b/src/mainboard/asrock/z87_extreme3/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..d592fa6243cbb313b97194e0f90c6a3ff7e47334 GIT binary patch literal 6144 zcmeHJU2GIp6h3!mc6WAmX1X0JY*(nKKww*GJ8emAni^-@E$)_uZht71U|3*RL<^Jx z27eM(tr35s8$$>f0!<)BNF=-%UVK1f0ttkm5uz{3lOa499*8jpSkIlAT?kd!s6g8p3#VaAi+2iLPY8gr>?Pbe$?)iN3)#vFK2AO;@t7dnq1; znNSGcx(bkCY^K`M+}4)ZygfS_8K}ef;7VM!W!=WnY*Q?|?Zxd|#xT{L!07t*+0pFy z+U?m44h}yZMb4=yT{||8W^nnAP3yAb9mt6&8k-k4wk}3Ao10qNn_A4~R8`^T(=;21vl;CsWA~Qvu||xJj^Y51*@gqzZQ1dcvYAFr;T)$xmKXr@Kn1fHyV(MM znW?fAm#v759wtSZRm(6YSsIgin3R#M1heWGCM9dWgo`8$f}k-$0;nyvh%|EB4O)yr$)J5X27@r=*)zh z{u&q;BXCF*;HcOR%cL`K$dB-qKL{5IR|so-G9309@Hyc$;RnJmJ_UXw2(khyp_(v{ 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zZEbI`MjCF9g$NZk1C=oE{ntgE1?e2jNC$(J{4J*qR82|LGPm7_ChYO8;Oz}Agpp&t zXXwQLK(2+mWYHt=&Js#yf=>J^AO#s%#P-4!vGD}J?vgwlCZ813GM$0x3`}QWIs?-g Ic-S-W2ZfXlAOHXW literal 0 HcmV?d00001 diff --git a/src/mainboard/asrock/z87_extreme3/devicetree.cb b/src/mainboard/asrock/z87_extreme3/devicetree.cb new file mode 100644 index 0000000000..fe5c43b531 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/devicetree.cb @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PCIE2 + end + device pci 01.1 on # PCIE3 + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off # MEI #2 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0xc892 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 on # RP #6: PCIE1 x1 slot + subsystemid 0x1849 0x8c1a + end + device pci 1c.6 on # RP #7: ASM1083/1085 PCIe to PCI Bridge + subsystemid 0x1849 0x244e + end + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x3b # + ECP and EPP 1.9 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/asrock/z87_extreme3/dsdt.asl b/src/mainboard/asrock/z87_extreme3/dsdt.asl new file mode 100644 index 0000000000..17c44b6523 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads b/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads new file mode 100644 index 0000000000..cab2ff738c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- D-SUB + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_extreme3/gpio.c b/src/mainboard/asrock/z87_extreme3/gpio.c new file mode 100644 index 0000000000..54dd668fc0 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_extreme3/hda_verb.c b/src/mainboard/asrock/z87_extreme3/hda_verb.c new file mode 100644 index 0000000000..8c07b9822b --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1849c892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1849c892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_extreme3/romstage.c b/src/mainboard/asrock/z87_extreme3/romstage.c new file mode 100644 index 0000000000..52e7f0072c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/romstage.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};