rdc/r8610: Move to src/soc
Change-Id: I99e5d7f3b46c90ca863ddf6c186b5447d0c8e6f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14607 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Stefan Reinauer
parent
5caf89b9f8
commit
3b0f20ba70
9 changed files with 31 additions and 46 deletions
28
src/soc/rdc/r8610/Kconfig
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28
src/soc/rdc/r8610/Kconfig
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@ -0,0 +1,28 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOC_RDC_R8610
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bool
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ROMCC
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select LATE_CBMEM_INIT
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "soc/rdc/r8610/bootblock.c"
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depends on SOC_RDC_R8610
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23
src/soc/rdc/r8610/Makefile.inc
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23
src/soc/rdc/r8610/Makefile.inc
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
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## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOC_RDC_R8610),y)
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ramstage-y += northbridge.c
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ramstage-y += r8610.c
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endif
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26
src/soc/rdc/r8610/bootblock.c
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26
src/soc/rdc/r8610/bootblock.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/pci_def.h>
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static void bootblock_southbridge_init(void)
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{
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uint32_t tmp;
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tmp = pci_read_config32(PCI_DEV(0, 7, 0), 0x40);
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/* decode all flash ranges */
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pci_write_config32(PCI_DEV(0, 7, 0), 0x40, tmp | 0x07ff0000);
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}
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124
src/soc/rdc/r8610/northbridge.c
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124
src/soc/rdc/r8610/northbridge.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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*
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* Based on qemu-x86/northbridge.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <smbios.h>
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#include <cbmem.h>
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static unsigned long get_memory_size(void)
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{
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device_t nb_dev;
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u8 size;
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nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
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PCI_DEVICE_ID_RDC_R8610_NB, 0);
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size = pci_read_config8(nb_dev, 0x6d) & 0xf;
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return (2 * 1024) << size;
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}
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static void cpu_pci_domain_set_resources(device_t dev)
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{
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u32 pci_tolm = find_pci_tolm(dev->link_list);
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unsigned long tomk = 0, tolmk;
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int idx;
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tomk = get_memory_size();
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printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
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tomk, tomk / 1024);
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap the memory. */
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tolmk = tomk;
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}
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/* Report the memory regions. */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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set_top_of_ram(tomk * 1024);
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assign_resources(dev->link_list);
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}
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static void cpu_pci_domain_read_resources(struct device *dev)
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{
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pci_domain_read_resources(dev);
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}
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#if CONFIG_GENERATE_SMBIOS_TABLES
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static int rdc_get_smbios_data16(int handle, unsigned long *current)
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{
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struct smbios_type16 *t = (struct smbios_type16 *)*current;
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int len = sizeof(struct smbios_type16);
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memset(t, 0, sizeof(struct smbios_type16));
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t->type = SMBIOS_PHYS_MEMORY_ARRAY;
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t->handle = handle;
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t->length = len - 2;
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t->location = 3; /* Location: System Board */
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t->use = 3; /* System memory */
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t->memory_error_correction = 3; /* No error correction */
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t->maximum_capacity = get_memory_size();
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*current += len;
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return len;
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}
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static int rdc_get_smbios_data(device_t dev, int *handle,
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unsigned long *current)
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{
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int len;
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len = rdc_get_smbios_data16(*handle, current);
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*handle += 1;
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return len;
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}
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#endif
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static struct device_operations pci_domain_ops = {
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.read_resources = cpu_pci_domain_read_resources,
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.set_resources = cpu_pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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#if CONFIG_GENERATE_SMBIOS_TABLES
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.get_smbios_data = rdc_get_smbios_data,
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#endif
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};
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static void enable_dev(struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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/* Set the operations if it is a special bus type */
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dev->ops = &pci_domain_ops;
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}
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}
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struct chip_operations northbridge_rdc_r8610_ops = {
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CHIP_NAME("RDC R8610 Northbridge")
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.enable_dev = enable_dev,
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};
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116
src/soc/rdc/r8610/r8610.c
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116
src/soc/rdc/r8610/r8610.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/i8259.h>
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#include <stdlib.h>
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static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 };
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static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 };
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static void pci_routing_fixup(struct device *dev)
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{
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pci_assign_irqs(0, 0x8, enetIrqs);
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pci_assign_irqs(0, 0xa, usbIrqs);
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}
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static void r8610_init(struct device *dev)
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{
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device_t nb_dev;
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u32 tmp;
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printk(BIOS_DEBUG, "r8610 init\n");
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/* clear DMA? */
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outb(0x4, 0x8);
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outb(0x4, 0x10);
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outb(0xfc, 0x61);
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/* Set serial base */
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pci_write_config32(dev, 0x54, 0x3f8);
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/* serial IRQ disable, LPC disable,
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* COM2 goes to LPC, internal UART for COM1
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*/
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pci_write_config32(dev, 0x50, 0x84101012);
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/* Enable internal Port92, enable chipselect for flash */
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tmp = pci_read_config32(dev, 0x40);
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pci_write_config32(dev, 0x40, tmp | 0x07FF0600);
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/* buffer strength SB pins */
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pci_write_config32(dev, 0x5c, 0x2315);
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/* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9,
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* INTC 9, INTB 12, INTA INT10
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*/
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pci_write_config32(dev, 0x58, 0xdf0311b3);
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/* USB PHY control */
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nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
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PCI_DEVICE_ID_RDC_R8610_NB, 0);
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tmp = pci_read_config32(nb_dev, 0xc0);
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tmp |= 0x40000;
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pci_write_config32(nb_dev, 0xc0, tmp);
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setup_i8259();
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}
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static void r8610_read_resources(device_t dev)
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{
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struct resource *res;
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pci_dev_read_resources(dev);
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res = new_resource(dev, 1);
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res->base = 0x0UL;
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res->size = 0x1000UL;
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res->limit = 0xffffUL;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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/* Reserve space for flash */
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res = new_resource(dev, 2);
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res->base = 0xff800000;
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res->size = 8*1024*1024;
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res->limit = 0xffffffffUL;
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res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
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IORESOURCE_ASSIGNED;
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}
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static void southbridge_init(struct device *dev)
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{
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r8610_init(dev);
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pci_routing_fixup(dev);
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}
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static struct device_operations r8610_sb_ops = {
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.read_resources = r8610_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = &southbridge_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &r8610_sb_ops,
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.vendor = PCI_VENDOR_ID_RDC,
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.device = PCI_DEVICE_ID_RDC_R8610_SB,
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};
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