From 3b008bde8c8a00089d4e8ada724b34aa02845876 Mon Sep 17 00:00:00 2001 From: Bincai Liu Date: Fri, 4 Jul 2025 17:12:20 +0800 Subject: [PATCH] soc/mediatek/mt8196: Fix intermittent black screen issue Currently we set DP_PHY_DIG_TX_CTL_0 during the PHYD reset flow. However, that would cause the training to fail and result in intermittent black screen issues. As suggested by the eDP PHYD designer, the reset procedure should be refined by setting bit 0 of DP_PHY_DIG_SW_RST from 0 to 1 to reset the eDP PHYD status before training. DP_PHY_DIG_TX_CTL_0 controls the eDP PHYD lane count: setting BIT0 enables lane0, and setting BIT1 enables lane1. The eDP PHYD designer also recommends that when resetting PHYD, it is sufficient to set DP_GLB_SW_RST_PHYD and leave DP_PHY_DIG_TX_CTL_0 unchanged. After this change, this function is identical to the mt8189 implementation. Move dptx_hal_phyd_reset code to common for reuse. BUG=b:427119942 BRANCH:rauru TEST=Check the display function on Navi Change-Id: I07bd6203a2b957eea79d1431953b043820c00338 Signed-off-by: Jarried Lin Signed-off-by: Bincai Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/88450 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/dp/dptx_hal_v2.c | 9 +++++++++ src/soc/mediatek/mt8189/dptx_hal.c | 9 --------- src/soc/mediatek/mt8196/dptx_hal.c | 21 --------------------- 3 files changed, 9 insertions(+), 30 deletions(-) diff --git a/src/soc/mediatek/common/dp/dptx_hal_v2.c b/src/soc/mediatek/common/dp/dptx_hal_v2.c index 0833f2de62..628af99112 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_v2.c +++ b/src/soc/mediatek/common/dp/dptx_hal_v2.c @@ -339,3 +339,12 @@ void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool en mtk_dp_mask(mtk_dp, REG_3580_DP_TRANS_P0, (enable ? val : 0x0) << 8, POST_MISC_DATA_LANE_OV_DP_TRANS_4P_MASK); } + +void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) +{ + mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0)); + udelay(10); + mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0)); + + dptx_hal_reset_swing_preemphasis(mtk_dp); +} diff --git a/src/soc/mediatek/mt8189/dptx_hal.c b/src/soc/mediatek/mt8189/dptx_hal.c index 552f79b7cd..3fa3955f55 100644 --- a/src/soc/mediatek/mt8189/dptx_hal.c +++ b/src/soc/mediatek/mt8189/dptx_hal.c @@ -26,12 +26,3 @@ void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count) mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x44, GENMASK(4 + lane_count - 1, 4), GENMASK(7, 4)); } - -void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) -{ - mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0)); - udelay(10); - mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0)); - - dptx_hal_reset_swing_preemphasis(mtk_dp); -} diff --git a/src/soc/mediatek/mt8196/dptx_hal.c b/src/soc/mediatek/mt8196/dptx_hal.c index 110f5f1ada..9fe8571231 100644 --- a/src/soc/mediatek/mt8196/dptx_hal.c +++ b/src/soc/mediatek/mt8196/dptx_hal.c @@ -18,24 +18,3 @@ void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count) for (int i = 0; i < lane_count; i++) mtk_dp_phy_mask(mtk_dp, PHYD_DIG_GLB_OFFSET + 0x74, BIT(i), BIT(i)); } - -void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp) -{ - u32 val; - - mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, 0, BIT(0)); - udelay(10); - mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_SW_RST, BIT(0), BIT(0)); - val = mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0) & 0xF; - printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", val); - - while (val > 0) { - val >>= 1; - mtk_dp_phy_mask(mtk_dp, DP_PHY_DIG_TX_CTL_0, val, 0xF); - printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", val); - } - printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n", - mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0)); - - dptx_hal_reset_swing_preemphasis(mtk_dp); -}