soc/mediatek/common: Refactor mtk_dsi_dphy_timing

Refactor the MIPI DPHY implementation to improve modularity and
maintainability:
- Extract the dphy timing calculation to mtk_mipi_dphy_v1.c.
- Update Makefiles for multiple chips to include the new file.
- Enhance board-specific tuning by isolating timing configuration logic.

BUG=b:424782827
TEST=Build pass, boot ok, display ok

Change-Id: Ie0daa6e7b384a172ed483eda926e5acd1e3c539a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90358
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/dsi_common.c

@@ -76,24 +76,7 @@ static void mtk_dsi_dphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
 	u32 timcon0, timcon1, timcon2, timcon3;
 	u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz);
 
-	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
-	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
-	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
-			     timing->da_hs_prepare;
-	timing->da_hs_trail = timing->da_hs_prepare + 1;
-
-	timing->ta_go = 4 * timing->lpx - 2;
-	timing->ta_sure = timing->lpx + 2;
-	timing->ta_get = 4 * timing->lpx;
-	timing->da_hs_exit = 2 * timing->lpx + 1;
-
-	timing->da_hs_sync = 1;
-
-	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
-	timing->clk_hs_post = timing->clk_hs_prepare + 8;
-	timing->clk_hs_trail = timing->clk_hs_prepare;
-	timing->clk_hs_zero = timing->clk_hs_trail * 4;
-	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
+	mtk_dsi_dphy_timing_calculation(data_rate_mhz, timing);
 
 	/* Allow board-specific tuning. */
 	mtk_dsi_override_phy_timing(timing);

src/soc/mediatek/common/include/soc/dsi_common.h

@@ -218,6 +218,7 @@ void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
 			     s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte);
 void mtk_dsi_cphy_disable_ck_mode(void);
 void mtk_dsi_dphy_disable_ck_mode(void);
+void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing);
 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands);

src/soc/mediatek/common/mtk_mipi_dphy_v1.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <device/mmio.h>
+#include <soc/dsi.h>
+
+void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing)
+{
+	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
+	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
+	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
+			     timing->da_hs_prepare;
+	timing->da_hs_trail = timing->da_hs_prepare + 1;
+
+	timing->ta_go = 4 * timing->lpx - 2;
+	timing->ta_sure = timing->lpx + 2;
+	timing->ta_get = 4 * timing->lpx;
+	timing->da_hs_exit = 2 * timing->lpx + 1;
+	timing->da_hs_sync = 1;
+
+	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
+	timing->clk_hs_post = timing->clk_hs_prepare + 8;
+	timing->clk_hs_trail = timing->clk_hs_prepare;
+	timing->clk_hs_zero = timing->clk_hs_trail * 4;
+	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
+}

src/soc/mediatek/mt8173/Makefile.mk

@@ -72,6 +72,7 @@ ramstage-y += ../common/usb.c usb.c
 
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/dsi_common.c dsi.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 
 BL31_MAKEARGS += PLAT=mt8173
 

src/soc/mediatek/mt8183/Makefile.mk

@@ -50,6 +50,7 @@ ramstage-y += emi.c
 ramstage-y += ../common/auxadc.c
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/gpio_eint_v1.c ../common/gpio.c gpio.c
 ramstage-y += ../common/i2c.c i2c.c
 ramstage-y += ../common/mcu.c

src/soc/mediatek/mt8186/Makefile.mk

@@ -41,6 +41,7 @@ ramstage-y += ../common/devapc.c devapc.c
 ramstage-y += ../common/dfd.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c

src/soc/mediatek/mt8188/Makefile.mk

@@ -46,6 +46,7 @@ ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c

src/soc/mediatek/mt8189/Makefile.mk

@@ -57,6 +57,7 @@ ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
 ramstage-y += ../common/mtk_mipi_cphy.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/pi_image.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c

src/soc/mediatek/mt8192/Makefile.mk

@@ -41,6 +41,7 @@ ramstage-y += ../common/dfd.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dpm_v1.c
 ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c ../common/mtk_mipi_dphy.c
+ramstage-y += ../common/mtk_mipi_dphy_v1.c
 ramstage-y += ../common/l2c_ops.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c