From 3aa312e4c976ffca506d9b580ecce443a8a330b5 Mon Sep 17 00:00:00 2001 From: Xiandong Wang Date: Fri, 10 Oct 2025 11:16:24 +0800 Subject: [PATCH] soc/mediatek/mt8189: Add DSI path support and update mutex Previously, only the EDP display path was supported due to incorrect mutex bitfield assignments and incomplete main path setup logic. This commit corrects the mutex bitfield assignments after reviewing the datasheet, and updates the main path setup logic to enable support for both EDP and DSI display paths, improving overall compatibility. BUG=b:433422905,b:428854543 BRANCH=skywalker TEST=Check log on padme mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz Signed-off-by: Xiandong Wang Change-Id: Ic3f901b9dff0a7ec9188212d2311b8394cf5c0e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/89566 Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8189/ddp.c | 14 ++++++++++---- src/soc/mediatek/mt8189/include/soc/ddp.h | 16 ++++++++++------ 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/soc/mediatek/mt8189/ddp.c b/src/soc/mediatek/mt8189/ddp.c index f7bdc7f835..1d5630736c 100644 --- a/src/soc/mediatek/mt8189/ddp.c +++ b/src/soc/mediatek/mt8189/ddp.c @@ -14,7 +14,8 @@ static void disp_config_main_path_connection(enum disp_path_sel path) write32(&mmsys_cfg->disp_rdma0_sel_in, 0x1); write32(&mmsys_cfg->disp_rdma0_rsz0_sout_sel, 0x0); write32(&mmsys_cfg->ovl_pq_out_cross1_mout_en, 0x10); - write32(&mmsys_cfg->comp_out_cross4_mout_en, 0x02); + write32(&mmsys_cfg->comp_out_cross4_mout_en, + path == DISP_PATH_EDP ? 0x02 : 0x01); printk(BIOS_DEBUG, "%s: bgclr_mout_en: %#x ovl0_mout_en: %#x sel_in: %#x sout_sel: %#x" "cross1_mout_en: %#x cross4_mout_en: %#x\n", @@ -28,11 +29,16 @@ static void disp_config_main_path_connection(enum disp_path_sel path) static void disp_config_main_path_mutex(enum disp_path_sel path) { - write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + u32 val; + + val = path == DISP_PATH_EDP ? MUTEX_MOD_MAIN_PATH : MUTEX_MOD_MAIN_DSI_PATH; + write32(&disp_mutex->mutex[0].mod, val); /* Clock source from DVO0 */ - write32(&disp_mutex->mutex[0].ctl, - MUTEX_SOF_DVO | (MUTEX_SOF_DVO << 7)); + val = path == DISP_PATH_EDP ? (MUTEX_SOF_DVO | (MUTEX_SOF_DVO << 7)) : + (MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 7)); + write32(&disp_mutex->mutex[0].ctl, val); + write32(&disp_mutex->mutex[0].en, BIT(0)); printk(BIOS_DEBUG, "%s: mutex_mod: %#x ctl %#x\n", __func__, read32(&disp_mutex->mutex[0].mod), read32(&disp_mutex->mutex[0].ctl)); diff --git a/src/soc/mediatek/mt8189/include/soc/ddp.h b/src/soc/mediatek/mt8189/include/soc/ddp.h index feb975af8b..a9d02f75d9 100644 --- a/src/soc/mediatek/mt8189/include/soc/ddp.h +++ b/src/soc/mediatek/mt8189/include/soc/ddp.h @@ -268,15 +268,19 @@ DEFINE_BIT(PQ_CFG_ENGINE_EN, 1) enum { MUTEX_MOD_DISP_OVL0 = BIT(0), MUTEX_MOD_DISP_RDMA0 = BIT(4), - MUTEX_MOD_DISP_COLOR0 = BIT(4), - MUTEX_MOD_DISP_CCORR0 = BIT(5), - MUTEX_MOD_DISP_CCORR2 = BIT(6), - MUTEX_MOD_DISP_AAL0 = BIT(7), - MUTEX_MOD_DISP_GAMMA0 = BIT(8), - MUTEX_MOD_DISP_DITHER0 = BIT(10), + MUTEX_MOD_DISP_COLOR0 = BIT(6), + MUTEX_MOD_DISP_CCORR0 = BIT(8), + MUTEX_MOD_DISP_CCORR2 = BIT(10), + MUTEX_MOD_DISP_AAL0 = BIT(12), + MUTEX_MOD_DISP_GAMMA0 = BIT(14), + MUTEX_MOD_DISP_DITHER0 = BIT(16), + MUTEX_MOD_DISP_DSI0 = BIT(22), MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_RDMA0, + MUTEX_MOD_MAIN_DSI_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_DSI0, }; enum {